Hi, I am having trouble using a generate statement to build thearchitecture for

Question

Hi, I am having trouble using a generate statement to build thearchitecture for an entity that checks for parity. I have beengiven a file with all component definitions such that for achain with 7 xor's, it is the following:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xor2 is
    port(
        in1, in2:     in     std_logic;
       out1     :    out     std_logic );
end entity xor2;

architecture primitive of xor2 is
begin
       out1 <= in1 xor in2 after 3ns;
end architecture primitive;
******************************
My code:
--Implementation of chain2 using Generic
--the ENTITYdeclaration for ParityCheck contains a clause GENERICby it’s
--PORT definition. The GENERIC clause is a way to pass values toinstances
-- of an ENTITY. The value specified in the ENTITY declaration issimply
--the default value of the GENERIC parameter. We pass a specificvalue of
--the parameter to an ENTITYobject whenever we instantiate theENTITY.

architecture Chain2 of ParityCheck is
signal GS(I) : in STD_LOGIC;

begin
     --width (max value is integer with a valueof 8)
   X0r: for I in 6 downto 0 generate
      SI: entity work.xor2 port map (input(I), input(I), GS(I));  
   end generate x0r;
  
   X1r: for I in 5 downto 0 generate
      SI: entity work.xor2 port map(input(I), GS(I), GS(I));
   end generate X1r;
  
   X2r: for I in 4 downto 0 generate
      SI: entity work.xor2 port map(input(I), GS(I), GS(I));
   end generate X2r;

   X3r: for I in 3 downto 0 generate
      SI: entity work.xor2 port map (input(I),GS(I), GS(I));
   end generate X3r;
   
   X4r: for I in 2 downto 0 generate
      SI: entity work.xor2 port map(input(I), GS(I), GS(I));
   end generate X4r;
  
   X5r: for I in 1 downto 0 generate
      SI: entity work.xor2 port map(input(I), GS(I), GS(I));
   end generate X5r;
  
   X6r: for I in 0 downto 0 generate
      SI: entity work.xor2 port map(input(I), GS(I), output);
   end generate X6r;

end architecture Chain2;   

*******************
Is this how you do use generate statements?
I tried simulating it, but it seems I have errors.....
Thanks

Explanation / Answer

what VHDL software are you using ? if youhave a way of posting your code so that it iseasy to read I will take a shot .... let me know

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