Design a parity checker logical circuit with three inputs A,B, and C and only 1

Question

Design a parity checker logical circuit with three inputs A,B, and C and only 1 output Y. Y should be high only whenthere are an even number of '1's in the input.
Ex: when ABC=101, Y=1 and when ABC=001, Y=0
A) find the truth table & expression of the outputcircuit
B) simplify the output expression
C) realize the circuit using only AND, OR, and NOT gates
D) realize the circuit using only NAND gates andinverters
E) which of the above circuits implements a better solutionfor 1-number of chips used
                                                                                             2-totalpropagation delay I got a very helpful answer earlier, but according to myprofessor, in the truth table, 000 counts as an even number of1s Design a parity checker logical circuit with three inputs A,B, and C and only 1 output Y. Y should be high only whenthere are an even number of '1's in the input.
Ex: when ABC=101, Y=1 and when ABC=001, Y=0 A) find the truth table & expression of the outputcircuit B) simplify the output expression C) realize the circuit using only AND, OR, and NOT gates D) realize the circuit using only NAND gates andinverters E) which of the above circuits implements a better solutionfor 1-number of chips used                                                                                              2-totalpropagation delay I got a very helpful answer earlier, but according to myprofessor, in the truth table, 000 counts as an even number of1s

Explanation / Answer

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