Design a circuit, and model using HDL that 1) adds two three bit unsigned binary

Question

Design a circuit, and model using HDL that 1) adds two three bit unsigned binary numbers, 2) includes a flag to determine when a overflow occurs, and 3) includes a flag indicating whether the resulting sum is even or odd.
You should create a test bench and test your design by completing the sums below:
000 + 000
010 + 001
011 + 011
111 + 001
Your inputs and outputs should be defined as follows:
A2, A1, A0 : B2, B1, B0 Represent your binary inputs, 0 defines least significant bit
Sum Represents the output sum
O Represents the overflow flas, no overflow =0 P Represents the even/odd flag, even = 0
*NOTE: I need the HDL file and a timing diagram used

Explanation / Answer

module adder (sum,o,p,a,b) ; input [2:0] a,b; output [2:0] reg sum; output reg p,v; always @(a,b) begin {o,sum}

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