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Consider a non-pipelined chip in which each instruction can be executed in 140 n

ID: 1832704 • Letter: C

Question

Consider a non-pipelined chip in which each instruction can be executed in 140 ns. A chip design company comes up with a new 4-stage pipelined design to execute instructions such that stage s1 takes 30 ns, s2 takes 30 ns, s3 takes 50 ns and s4 takes 30 ns of processing time.
a. Determine the time taken to execute the first instruction I1 in both the pipelined and non-pipelined cases. Also determine the time (i.e., how long it takes to execute them) at which the second instruction I2 and third instruction I3 finish execution in the pipelined and non-pipelined cases. Explain your answer.
b.Next, given the above conditions determine the maximum possible speedup in the throughput of the pipelined machine over the non-pipelined version. Explain your answer.

Explanation / Answer

I1 first instruction takes time to execute in non pipelined structure = 140ns in pipelined structure= 30+30+50+30=170 ns I2 second instruction takes time to execute in non pipelined structure = 140+140=280ns because every instruction takes 140ns to execute in pipelined structure= 170+30=200 ns because when the I1 is executing, I2 will be in s3 stage and it will take only 30 ns more after the execution of I1. I3 second instruction takes time to execute in non pipelined structure = 140+140+140=420ns because every instruction takes 140ns to execute in pipelined structure=200 + 30= 230 ns because when the I2 is executing, I3 will be in s3 stage and it will take only 30 ns more after the execution of I2. b)ans exact time to execute 3 instruction non pipeline = 3*140=420ns in pipeline = 230ns speed up = 420/230=1.826 hence pipelined structure is 1.826 times faster than non pipelined structure. for detailed analysis , please follow http://webdocs.cs.ualberta.ca/~amaral/courses/429/webslides/Topic3-Pipelining/sld020.htm

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