Create a digital lock in VHDL using the following constraints: 1. Use button btn

Question

Create a digital lock in VHDL using the following constraints: 1. Use button btnC to reset the circuit. 2. Use button btnU to set the circuit into the normal mode. 3. Use button btnD to set the circuit into the programming mode 4. Use sw3 - sw0 to create a single digit BCD number. Then use btnL to make the circuit read and store this number. 5. After a sequence of three numbers are read into the circuit, use button btnR to store the sequence as the key in the programming mode, or to compare the input sequence against what is stored in the circuit for authentication in the normal mode. 6. Every time a number is read into the circuit by pressing button btnL, this number is shown on the 7-segment display. 7. In the normal mode, once the input sequence is authenticated, led15 - led0 all light up. 8. If authentication attempts fail 3 times consecutively, the circuit transitions to the locked mode. Once the circuit is in the locked state, all leds light off, and the 7-segment display shows ----.

Explanation / Answer

ANSWER:

The safe`s electronics receives inputs from the front panel & provide signals to the seven segment displays & to a motorized bolt. When the bolt`s motor is actuated to turn in one direction, it unlocks the safe door [5]. The block diagram of electronic safe lock and it is consists of six design entities [7]. U1: ose_decoder_fsm U5&U6: bcd_7seg U2: bcd_2dec U3: digit_compare U4: master_fsm.

U1&U4 are both fsms which together control the operation of the system. U2 is two digits modulo BCD counter. U5&U6 convert each BCD digit from U2 to a seven segment code. In theory, the control portion of the electronic safe could be designed as a single fsm. However, it simplifies defining the operation of electronic safe to partition the control function into two cooperating fsms. Ose fsm is component of ose_decoder_fsm. It has limited and very specific functions. The other fsm is master_fsm. This fsm controls the overall operation of the safe.

U1: OSE_DECODER_FSM :We can design a four time decoder that enables the counter to count once for each combination of A&B. this increases the effective resolution of OSE and decoder combination by a factor of 4, compared to simply counting positive edges of A(or B) directly[4].

U2: BCD_2DEC :This two-digit BCD counter counts from 00 to 31 and then rolls over to 00. The count direction can be up or down. The counter has two counts enable inputs: both must be asserted for the counter to count. Integer variables are used to store the count.

U3: DIGIT_COMPARE

This block is used to compare the two digits being entered by the user. The entity digit_compare has bcd0, bcd1 and num_sel as inputs and num_eq as an output. The architecture body compares the three combinations entered by the user. When the entered combination is correct the output signal num_eq becomes equal to 1 otherwise it remains equal to 0.

U4:MASTER_FSM :The master_fsm is the most important and useful block of electronic safe. This block controls the functioning of all the signals and blocks. In other words we can say that it is the heart of the electronic safe[9]. The overall characteristics of the safe are determined by component master_fsm.

U5&U6:BCD_7SEG

An often used decoder function is a BCD to seven-segment decoder [8]. This decoder takes as its inputs four bits that represent a binary coded decimal value and generates a 7-bit output to drive a seven segment LED. If the BCD input has a value from 0 to 9, the output consists of the value needed to display the corresponding decimal digit. If the BCD input is greater than 9, all the outputs are don`t care. Since these input values should not occur.

A final point is that when a VHDL model is translated into the “gates and wires” that are mapped onto a programmable logic device such as CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being. When implementing the circuit in anti-fuse type FPGA, it is an advantage that the configuration file in memory is not necessary. In this case it is already verified that the circuit will be fully functional.

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