Given the Verilog code segment below, which statement is not true? reg q; always

Question

Given the Verilog code segment below, which statement is not true? reg q; always @(posedge clock or posedge reset) begin if (reset) qlessthan=0; else if (set) q lessthan= 1; end When both reset and set are zero, q doesnprimet change. The reset is synchronous. Non-blocking assignments are used in this code. The set is synchronous Which statements are true for the clock counter implementation shown below? The counter should count from 00 to 59 and back to 00. Select all that apply always@(reset) begin ... end always@(posedge clk) begin ... end Asynchronous reset is asserted when the counter output is 59. Synchronous reset is asserted when the counter output is 59. We can use only one 6 bit variable to keep track of the count None of the above

Explanation / Answer

(i)

option C is correct, expect this remaining all are reled to code

(ii)

options A and B are correct

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