The code below should implement a simple four state FSM whi bit synchronous coun

Question

The code below should implement a simple four state FSM whi bit synchronous counter when the FSM is in state 2'b10. An a signal is used to force both the state machine and the counter to a it is high. Identify the major problem with this code when synth solution to fix the problem. You can define a new control signal module simple_fsm(clk, reset, count); input reset, clk; output [3:0] count; reg [3:0] count; reg [1:0] state; reg [1 0] next; always @ (posedge clk or posedge reset) begin if (reset) begin state

Explanation / Answer

In this code, count is incremented by 1 for every 3 clock periods. But count should increment for every clock period. This is giving wrong functionality.

So, design it only by using two states.

module simple_fsm(clk,reset,count);

input clk,reset;

output reg [3:0] count;

reg state,next;

always @(posedge clk,posedge reset)

begin

if (reset)

state <= 1'b0;

else

state <= next;

end

always @(state,reset)

begin

if(reset)

count = 4'b0000;

else

case(state)

1'b0: next = 1'b1;

1'b1: begin

count = count + 4'd1;

if (count == 4'd15)

next = 1'b0;

end

endcase

end

endmodule

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