Basic Pipelining Consider the following code fragment: LW Rl, 0(R2) DADDI Rl, Rl

Question

Basic Pipelining Consider the following code fragment: LW Rl, 0(R2) DADDI Rl, Rl, 1 SW Rl, 0(R2) DADDI R2, R2, 4 DADDI R4, R4, -4 BNEZ R4, Loop Consider the standard 5 stage pipeline machine (IF ID EX MEM WB). Assume the initial value of R4 is 396 and all memory accesses hit in the cache. Show the timing of the above code fragment for one iteration as well as for the load of the second iteration. For this part, assume there is no forwarding or bypassing hardware. Assume a register write occurs in the first half of the cycle and a register read occurs in the last half of the cycle. Also, assume that branches are resolved in the memory stage and are handled by flushing the pipeline. Use a pipeline timing chart to show the timing as below (expand the chart if you need more cycles). How many cycles does this loop take to complete (for all iterations, not just one iteration)?

Explanation / Answer

THE number of cycles to complete one iteration is 12

total number of iterations are 99

after completing the second iteration it takes 20 clock cycles

and after completing the third iteration it takes 28 clock cycles

so the total number of clock cycles taken to complete all iterations is 1*12+ 98*8 = 796

instruction c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 LW R1, 0(R2) F D X M W DADDI R1,R1,#1 F D S X M W SW R1,0(R2) F S D X M W DADDI R2,R2,#4 F D X M W DADDI R4,R4,#-4 F D X M W BENZ R4,Loop F S D X M W LW R1, 0(R2) F D X M W

Related Questions

Navigate

• Browse (All)
• Browse B
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.