What causes a register to enter a metastable state? failure to satisfy a data se

Question

What causes a register to enter a metastable state? failure to satisfy a data setup time requirement exceeding the maximum recommended VCC voltage excessive fanout none of the above Consider a 2-bit binary counter. What is the count sequence if the output is taken from the Q-bar outputs instead of the Q outputs? 0, 1.2, 3, 0, 1.... 0, 1.2, 3, 4, 0..... 3, 2, 1, 0, 3..... none of the above Which of the following are invalid inputs for a D-latch? D = '0' D = '1' A D-latch doesn't have any invalid inputs What is worst case propagation delay (D input to Q output) of a 74LVClg373 latch operating with VCC = 1.8V? 1 ns 2 ns 4 ns 15 ns The output of a sequential circuit is a function of the current input and past inputs. TRUE FALSE

Explanation / Answer

14. Option a is the answer because the input time must be long enough to setup the data and hold it ( setup time+ hold time)

15. The output sequence is 3,2,1,0,3,2,1,0.....

When Q bar outputs are considered,the counter simply becomes a down counter

16. A D - latch is also called transparent latch which means output is the input itself.

So there is no chance of having an invalid input for a D - latch

17. In a D latch input appears at the output. There will be minimum propogation delay .So it is 1 NS

18. TRUE. It has some memory to store the past inputs. It uses them along with present inputs in calculating the present state output

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