Verilog Rotate right not outputting any values please help, I have my code and t
ID: 2080059 • Letter: V
Question
Verilog Rotate right not outputting any values please help, I have my code and test bench below
module rotate_right (a,b,out);
input [3:0] a,b;
output reg [3:0] out;
initial begin
if (b == 4'b0000)
begin
out = a[3:0];
end
else if (b == 4'b0001)
begin
out = {a[2:0], a[3]};
end
else if (b == 4'b0010)
begin
out = {a[1:0], a[3:2]};
end
else if (b == 4'b0011)
begin
out = {a[0], a[3:1]};
end
else if (b == 4'b0100)
begin
out = a[3:0];
end
else if (b == 4'b0101)
begin
out = {a[2:0], a[3]};
end
else if (b == 4'b0110)
begin
out = {a[1:0], a[3:2]};
end
else if (b == 4'b0111)
begin
out = {a[0], a[3:2]};
end
else if (b == 4'b1000)
begin
out = a[3:2];
end
else if (b == 4'b1001)
begin
out = {a[2:0], a[3]};
end
else if (b == 4'b1010)
begin
out = {a[1:0], a[3:2]};
end
else if (b == 4'b1011)
begin
out = {a[0], a[3:1]};
end
else if (b == 4'b1100)
begin
out = {a[1:0], a[3:2]};
end
else if (b == 4'b1101)
begin
out = {a[2:0], a[3]};
end
else if (b == 4'b1110)
begin
out = {a[1:0], a[3:2]};
end
else if (b == 4'b1111)
begin
out = {a[0], a[3:1]};
end
end
endmodule
module rotate_right_test;
reg [3:0] a,b;
wire [3:0] out;
rotate_right uut (.a(a),.b(b),.out(out));
initial begin
#100 a = 4'b1100;
b = 4'b0101;
#100 a = 4'b0101;
b = 4'b0101;
end
Explanation / Answer
Hi,
Here the problem is because of using initial block in the code.Since an initial block is invoked at 0 simulation time and executes sequentially.After execution of last statement it terminates the simulation.In your test bench you are applying inputs with a delay of 100,in the meanwhile the initial block in the code has completed execution .So use an always block with the inputs in the sensitivity list in your code instead of an initial block .Now as the inputs change in the test bench the always block is invoked and you will get your required output.
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