Compute the impulse response (h[n]) of the given systems for n = 0:1:40. (Using

Question

Compute the impulse response (h[n]) of the given systems for n = 0:1:40. (Using filter command Compute the output of the systems with using the impulse response. Compute the output of the systems without using the impulse response for the given inputs Plot the impulsive response (h[n]), the given input sequence (x[n]), and outputs (using conv and filter functions) on a sheet of a paper for each problem. (Use subplot and stem commands.) y[n] = 1/3 y[n - 1] + x[n] x[n] = 2 times (0.9)^n u(n - 20) Write signals for n = 0: 1:40. Y[n] + 0.7y[n - 1] - 0.45 y[n - 2] - 0.6 y[n - 3] = 0.8x[n] - 0.44x[n - 1] + 0.36x[n - 2] + 0.02x[n - 3] x[n] = sin(n pi/10)u(n - 20) Write signals for n = 0: 1:40.

Explanation / Answer

In this lecture you will learn the following • Introduction • Logical Effort of an Inverter • Logical Effort of NAND Gate • Logical Effort of NOR Gate • Logical Effort of XOR Gate • Logic Effort Calculation of few Mixed Circuits • Delay Plot 22.1 Introduction The method of logical effort is an easy way to estimate delay in a CMOS circuit. We can select the fastest candidate by comparing delay estimates of different logic structures. The method also specifies the proper number of logic stages on a path and the best transistor sizes for the logic gates. Because the method is easy to use, it is ideal for evaluating alternatives in the early stages of a design and provides a good staring point for more intricate optimizations. It is founded on a simple model of the delay through a single MOS logic gate. The model describes delays caused by the capacitive load that the logic gate drives and by the topology of the logic gate. Clearly as the load increases, the delay increases, but the delay also depends on the logic function of the gate. Inverters, the simplest logic gates, drive loads best and are often used as amplifiers to drive large capacitances. Logic gates that compute other functions require more transistors, some of which are connected in series, making them poorer than inverters at driving current. Thus a NAND gate has more delay than an inverter with similar transistor sizes that drives the same load. The method of logical effort quantifies these effects to simplify delay analysis for individual logic gates and multistage logic networks.

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