true and false about verilog 21. Named events are synthesizable. 22. Some specia
ID: 2080298 • Letter: T
Question
true and false about verilog
21. Named events are synthesizable.
22. Some special hardware can be implemented to detect the value "x".
23. "casex" and "casez" support dont care values in both case branch expression and case expression.
24. Procedural assignment assigns values to register variables.
25. "?" is alternative for "x" in a casez branch expression.
26. A net does not store value (except trireg) unless it is driven.
27. By default, Verilog simulation time unit is unspecified.
28. Level sensitive latch can be described using an if statement.
29. Asynchronous feedback is always encouraged in Verilog HDL code.
Explanation / Answer
21. Named events are synthesizable.= FALSE
As events come under non-synthesizable
22. Some special hardware can be implemented to detect the value "x"=TRUE
Generally An X bit might be a 0, 1, Z, or in transition. We can set bits to be X in situations where we don’t care what the value is. This can help catch bugs and improve synthesis quality. A wire is used to detect them
23. "casex" and "casez" support dont care values in both case branch expression and case expression.= TRUE
Thay support don’t care values in either the case expression and/or the case item when doing case comparison.
24. Procedural assignment assigns values to register variables=TRUE
The procedural assignment, which assigns values to variables
25."?" is alternative for "x" in a casez branch expression=FALSE
Only "z" and "?" are allowed
26. A net does not store value (except trireg) unless it is driven=TRUE
They do not store values but there is only one exception - trireg, which stores a previously assigned value
27. By default, Verilog simulation time unit is unspecified= TRUE
The timescale line is very important in the verilog simulation, because there are no any default delays specified by the verilog
28. Level sensitive latch can be described using an if statement = TRUE
Latch-Level sensitive is described by if statement
29. Asynchronous feedback is always encouraged in Verilog HDL code=FALSE
Because it may reset
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