Determine the maximum gate delay through your final ALU circuit assuming each ga

Question

Determine the maximum gate delay through your final ALU circuit assuming each gate has a delay of 1 unit. Highlight the critical path on the gate-level schematic.

I understand the maxiumum gate delay can be sought out by obtaining the longest way from input to output assuming each gate delay has a delay of one unit. Is the path i created correct for the maximum gate delay for this schematic? If it is incorrect please provide corrected version with an explanation. Thank you!

Explanation / Answer

Your observation for critical data path is absolutely correct.

There will be total 10 unit of gate delay for the critical path, the maximum delay path of the circuit.

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