So this a devleoped Track-Hold circuit and there is few thing I don\'t understan

Question

So this a devleoped Track-Hold circuit and there is few thing I don't understand about concept of this circuit.

In the textbook, it is written, " when Q1 turns off, there will still be charge injection to the left side of , which will
cause the output voltage of opamp 2 to have a positive hold step, but this hold step will be just a dc offset and will
be signal independent. In other words, the charge injection due to will cause some dc offset but no distortion. In
addition, the sampling time will not change because of the finite slopes of the sampling-clock waveform."

So my question is, How does Q1 leads postive hold step? isn't it delta(V) = - (Cox * W * L (Veff)) / (2*Chold)? and my assumption is that Q1(NMOS) is placed opposite direction which leads postive hold step instead of negative hold step. Is it correct? (source is connected to input)

and how does hold step will be signal independent?

Lastly, how does this circuit's sampling time will not be changed?

So in textbook answer, there will be still sampling time changing in Q1(postive clock) but not in Q3(negative clock cycle) because ground connection of Q3 which leads negative voltage pulse.
Could you explain in detail? I don't understand how does ground connection results negative voltage pulse and how does it ends up getting no sampling time change.

Thank you in advance! :)

Analog Integrated Circuit Design (2nd Edition) Bookmark Show all steps: a ON EE Chapter 11, Problem 6P Step-by-step solution Chapter 1 Chapter 2 Chapter 3 v Step 1 of 4 A Chapter 4 Draw the following circuit diagram: Chapter 5 Chapter 6 am i Chapter 7 v Chapter 8 Chapter 9 pamp 2 Chapter 10 v Chapter 11 A Figure 1: Sample and hold circuit

Explanation / Answer

Hold step denotes the voltage error during transition

Signal independent because the second opamp has a larger gain as compared to signal variations which will lead to negligible dependency on the signal.

both position of the opamp and signal independence play a major part in positive hold step

Circuit sampling time will not change as the finite slopes of clock waveform are signal independent

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