A) Write VHDL code for an 8-bit pseudo-random number generator. A pseudorandom n
ID: 2081567 • Letter: A
Question
A) Write VHDL code for an 8-bit pseudo-random number generator. A pseudorandom number generator is an algorithm for generating a sequence of numbers whose properties approximate the properties of sequences of random numbers. The PRNG generated sequence is not truly random, because it is completely determined by a relatively small set of initial values. (Source – Wikipedia). Your component should have the below input and output pins. 1. Input pins: - clock, Reset. 2. 8 bit Output: - q. Note: The ( q(4) , q(3) , q(2) , q(0) ) signals of the register are xored to generate a new value, which is fed back to the serial-in port of the shift register. Assume that the initial state (a seed) of register is "00000001". You can use a constant to define the initial value.
B) Write a test bench (up to 8 sequences) to check the correctness of the code before running the synthesis and Implementation.
Explanation / Answer
library ieee;
use ieee.std_logic_1164.all;
entity prng_shift is
port(CLK, RST : in std_logic;
SO : out std_logic_vector(7 downto 0));
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (CLK,RST)
begin
if(RST = '1') then
tmp <= "00000000";
elsif (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= tmp(4) ^ tmp(3) ^ tmp(2) ^ tmp(0);
end if;
end process;
SO <= tmp;
end archi;
library ieee;
use ieee.std_logic_1164.all;
entity prng_shift _tb is
end prng_shift _tb;
architecture TB_ARCHITECTURE of prng_shift _tb is
component prng_shift
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
SO : out STD_LOGIC_VECTOR(7 downto 0) );
end component;
signal CLK : STD_LOGIC;
signal RST : STD_LOGIC;
signal SO : STD_LOGIC_VECTOR(7 downto 0);
begin
UUT : register_design
port map (
CLK => CLK,
RST => RST,
SO => SO
);
CLK_GEN: process
begin
CLK <= '0';
wait for 5 ns;
CLK <= '1';
wait for 5 ns;
end process;
stimuli : process
begin
RST <= '1' after 70 ns;
RST <= '0' after 80 ns;
wait;
end process;
end TB_ARCHITECTURE;
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