design and emulate a clock divider circuit to divide a 50MHz down to 1 Hz. assig

Question

design and emulate a clock divider circuit to divide a 50MHz down to 1 Hz. assign the input clock to the 50MHz pin on DE-2 board i. Design and emulate a clock divider circuit to divide a 50 MHz down to 1Hz. Assign the input clock to the 50 MHz pin on DE-2 board (CLOCK 50) and the output to a LED. 2. Design and emulate a synchronous counter that counts from 0 to 6. This circuit should use 74163 and display the result on a 7-segment LED. Assign the input clock to a pulser switch. 3. Follow the instructions in procedure 2 of Chapter 9 to design and emulate a sequencer using J-K flip-flops. Assign the cycle-selector input to a switch and the input clock to a pulser switch. Display the result using a 7-segment LED

Explanation / Answer

// Clock divider circuit // From 50 MHz to 1 Hz with %50 duty cycle module clk_div(Clk_in, Clk_out); // input ports input Clk_in; // output ports output reg Clk_out; // counter size calculation according to input and output frequencies parameter sys_clk = 50000000; // 50 MHz system clock parameter clk_out = 1; // 1 MHz clock output parameter max = sys_clk / (2*clk_out); // max-counter size reg [4:0]counter = 0; // 5-bit counter size always@(posedge Clk_in) begin if (counter == max-1) begin counter

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