Question 4 Indicate how the VHDL program in the below must be modified if the Y

Question

Question 4

Indicate how the VHDL program in the below must be modified if the Y outputs are floating when the select inputs are 11.

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity multiplexer33 is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
C : in STD_LOGIC_VECTOR (2 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end multiplexer33;

architecture arch of multiplexer33 is

begin
with S select
Y <= A when "00",
B when "01",
C when "10",
"000" when others;

Explanation / Answer

--The given vhdl code is for 4 to 1 mux with A, B and C as 3 inputs. Each input are 3 bits. The select line S selects a --particular input to be placed at output Y.

--when S=00, Y<=A;

--when S=01, Y<=B;

--when S=10, Y<=C;

--when S=11, Y<='ZZZ' since the 4th input is not defined the output becomes floating

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity multiplexer33 is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
C : in STD_LOGIC_VECTOR (2 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end multiplexer33;

architecture arch of multiplexer33 is

begin
with S select

Y <= A when "00",
B when "01",
C when "10",
'ZZZ' when "11";

end arch;

-- floating output ZZZ which is a high impedance state since nothing is defined for input when select line is 11

-- the above floating output can also be defined as 'ZZZ' when others both gives the same result

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