A CMOS inverter circuit is characterized by R_n = 600 Ohm; R_p = 590Ohm; V_DD =

Question

A CMOS inverter circuit is characterized by R_n = 600 Ohm; R_p = 590Ohm; V_DD = 5v. The output capacitance is measured to be C_out = 200 femto farads when Fan out is 1; it is known that the load accounts for 62 femto Farads in the value of C_out. (a) Calculate the values of t_LH and t_HL for the circuit with Fan Out = 1. (b) Calculate the values of t_LH and t_HL when Fan Out is increased to 3 identical loads. An integrated circuits factory initiates the processing of 5000 wafers per week, each wafers has 82 possible integrated circuits on it. If the estimated yield is 41%how many functional chips the factory produce in one week? What would be the weekly output if the yield were increased to 45%? Consider a chip that has dimension of 5000 mu m times 4000 pm. Estimate the fabrication yield Y, assuming a defect density of D = 0.5 cm^-2. What would the projected yield be if the design were shrunk to a size of 3900 mu m times 2900 mu m?

Explanation / Answer

8. solution:

a) solution :

For CMOS inverter the delay equation given as

for inverter p=1, g=1, h=1 there is no fan-out

tLH= tHL= 3RC(p+gh) where p,g,h are parasitic dealy, logical effort and electrical effort respectively

tLH=3RC(p+gh)= 2*3*590*200*10-15 = 0.354*2 nS = 0.708 nS

tHL= 3RC(p+gh)= 2*3*600*200*10-15= 0.72 nS

b) solution:

For CMOS inverter the delay equation after fan out is given as

tLH= tHL= 3RC(p+gh) where p,g,h are parasitic dealy, logical effort and electrical effort respectively

h= 3/1 so (p+gh)= 4 , for inverter p=1, g=1

tLH=3RC(p+gh)= 4*3*590*200*10-15 = 0.354*4 nS = 1.416 nS

tHL= 3RC(p+gh)= 4*3*600*200*10-15= 0.72 nS *2 = 1.44 nS

9) Solution:

if the estimated yield is 41% then the produced chips in one week

= 5000*82*(41/100) = 168100 chips

if the yield is increased to 45% then the chips produced will be

= 5000*82*(45/100)= 184500 chips

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