Suppose you wish to implement the following instruction in the MIPS datapath: DC

Question

Suppose you wish to implement the following instruction in the MIPS datapath:

DCB   rs, Label

DCB stands for Decrement and Branch. As with other branch instructions, Label is the branch target address, specified in the low order 16 bits of the instruction word. Register rs is in bits [25 . . 21] of the instruction word. This instruction works as follows.

Decrement the contents of register rs by 1.

If the result is zero, branch to the target address.

Update the contents of register rs with R[rs] – 1.

Assume that DCB is taken, so PC should be updated to the branch target address.

(a) Describe the changes you would make to implement this instruction in the MIPs single cycle datapath given in the handout.

(b) Specify the values of the following control variables to implement this instruction with the changes you made to the MIPS single cycle datapath given in the handout.

RegDst

ALUSrc

MemToReg

RegWrite

PCSrc

MemWrite

MemRead

ALUOp – just write the name of the operation here (Add, Sub, etc.):

(c) Describe the changes you would make to implement this instruction in the MIPS multicycle datapath given in the handout.

(d) Specify the complete finite state machine for the control necessary to implement DCB with the changes you made to the MIPS multicycle datapath given in the handout.

FIGURE 5.33 The complete datapath for the multicycle implementati en together with the necessary control ines. The control lines of Figure 532 are attached to the control unit, and the control and datapath elements needed to effect changes to the PC are included. The major additions from Figure 5.32 include the multiplexor used to select the source of a new PCvalue (at the top right); two gates used to combine the PC write signals (top left); and the control signals PCsource, PCWrite, and PCWriteCond. The POWriteCond signal is ANDed with the Zero output of the ALu to decide whether a branch should be taken; the resulting signal is ORed with the control signal PCWrite to generate the actual write control signal addition, the output of the IR is rearranged to send the lower 26 bits (the jump address to the logic used to select the next PC These 26 bits are shifted to the left by two, adding 2 loworder 0 bits; these 28 are then concatenated with the high-order 4 bits of the PC which has already been incremented

Explanation / Answer

a.)The control unit is responsible for setting all the control signals so that each instruction is executed properly.

— The control unit’s input is the 32-bit instruction word.

— The outputs are values for the blue control signals in the datapath.

Most of the signals can be generated from the instruction opcode alone, and not the entire 32-bit word.

To illustrate the relevant control signals, we will show the route that is taken through the datapath by R-type, lw, sw and beq instructions.

A datapath contains all the functional units and connections necessary to implement an instruction set architecture.

— For our single-cycle implementation, we use two separate memories, an ALU, some extra adders, and lots of multiplexers.

— MIPS is a 32-bit machine, so most of the buses are 32-bits wide. The control unit tells the datapath what to do, based on the instruction that’s currently being executed.

— Our processor has ten control signals that regulate the datapath.

— The control signals can be generated by a combinational circuit with the instruction’s 32-bit binary encoding as input. Next, we’ll see the performance limitations of this single-cycle machine and try to improve upon it.

Last time we saw a MIPS single-cycle datapath and control unit.

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