For a full answer and capture a thumbs up!! As part of the project requirement,

Question

For a full answer and capture a thumbs up!!
As part of the project requirement, following timing constraint must be satisfied: Main Main Side Main Main Side Side Third state: 25 seconds First state: 25 seconds Second stale: 4 seconds Fourth suale: 4 seconds minimum or as long as maximum or until there is no vehicle on there is no vehicle on side street side street The above timing requirements can be viewed as a high level state machine where the variables are: Vs Presence of vehicle on side street TL -Visibility of Long timer (25 sec) T. Visibility of Short timer (4 sec) Both timer(s) need to be appropriately triggered for successful operation of the TSC.

Explanation / Answer

library ieee;
use ieee.std_logic_1164.all;
entity tlc is
port (
clk, reset : in bit;
r, y, g : out bit);
end tlc;
architecture behavior of tlc is
TYPE state IS (R, Y, G);
CONSTANT timeMAX : INTEGER := 1500;
CONSTANT timeR : INTEGER := 1500;
CONSTANT timeY : INTEGER := 240;
CONSTANT timeG : INTEGER := 1500;
SIGNAL pr_state, next_state : state;
SIGNAL time: INTEGER RANGE 0 TO timeMAX;
BEGIN
PROCESS(clk, reset)
VARIABLE count : INTEGER RANGE 0 TO timeMAX;
BEGIN
IF (reset = '1') THEN pr_state <= R;
ELSIF (clk'event) AND (clk = '1') THEN count := count +1;
IF (count = time) THEN pr_state <= next_state;
count := 0;
END IF;
END IF;
END PROCESS;
PROCESS(pr_state)
BEGIN
CASE pr_state IS
WHEN R => r <=’1’; y <=‘0’; g <=‘0’;
time <= timeR;
next_state <= Y;
WHEN Y => r <=‘0’; y <=‘1’; g <=‘0’;
time <= timeY;
next_state <= G;
WHEN G => r <=‘0’; y <=‘0’; g <=‘1’;
time <= timeG;
next_state <= Y;
WHEN Y => r <=‘0’; y <=‘1’; g <=‘0’;
time <= timeY;
next_state <= R;
END CASE;
END PROCESS;
END behavior;

% Entity testbench

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