Implement a last in first out buffer. Its interface should match the FIFO in beh

Question

Implement a last in first out buffer. Its interface should match the FIFO in behavior. Your design should work across a range of bitwidths and array lengths. Your submission should include the file “lifo.sv” with the interface below.

// lifo.sv

module lifo #(

parameter int bW ,

parameter int eC

)

(

// push interface

input logic [bW-1:0] pushData,

input logic push,

output logic full,

// pop interface

output logic [bW-1:0] popData,

input logic pop,

output logic empty,

// Globals

input logic clk,

input logic rst );

endmodule

For example, an 8-bit 4-entry design's behavior would look like: clk rst push Data C7:o] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x08 0x09 0x0a push pop 0x01 0x02 0x03 0x04 0x05 0x05 0x04 0x03 0001 popData[7:0] full empty

Explanation / Answer

module LIFObuffer( dataIn, dataOut, RW, EN, Rst, EMPTY, FULL, Clk ); input [3:0] dataIn; input RW, EN, Rst, Clk; output reg EMPTY, FULL; output reg [3:0] dataOut; reg [3:0] stack_mem[0:3]; reg [2:0] SP; integer i; always @ (posedge Clk) begin if (EN==0); else begin if (Rst==1) begin SP = 3'd4; EMPTY = SP[2]; dataOut = 4'h0; for (i=0;i

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