Examine the VHDL code of SR Flip Flop given below and explain briefly meaning of

Question

Examine the VHDL code of SR Flip Flop given below and explain briefly meaning of pieces of code which were bolded. library ieee; use ieee. std_logic_1164.all; entity SR_FF is PORT(S, R, CLOCK: in std_logic; Q, QBAR: out std_logic); end SR_FF; Architecture behavioral of SR_FF is begin PROCESS (CLOCK) variable tmp: std_logic; begin if(CLOCK = '1' and CLOCK EVENT) then if(S = '0' and R = '0') then tmp:= tmp; elsif(S = '1' and R = '1') then tmp:= 'Z'; elsif(S = '0' and R = '1') then tmp:= '0'; else tmp:= '1'; end if; end if; Q

Explanation / Answer

library ieee;                           -- ieee library used.
use ieee.std_logic_1164.all;           -- The package in library std_logic_1164 is included.

entity SR_FF is                        -- This declare a module Entiry SR_FF.
PORT (S,R,CLOCK : in std_logic ;       -- declare input of the entity S,R and clock as std_logic.
   Q,QBAR : out std_logic);           -- declare output of the entity Q and QBAR as std_logic.
end SR_FF;

Architecture behaviooral of SR_FF is    -- Architecture of Entiry SR_FF begin here with name "behaviooral"
begin                                  
   PROCESS(CLOCK)                           -- Process started. CLOCK inside the bracket means SENSITIVE LIST. i.e. When CLOCK changes this process will execute.
   variable tmp : std_logic;               -- tmp variable of type std_logic is taken.
       begin                                   -- The process execution starts from here.
       if(CLOCK = '1' and CLOCK'EVENT) then   -- if condition checking for CLOCK = 1 and CLOCK'EVENT means The SR Filp Flop is Positive edge triggerd as the output will change at postive efge of clock.
          
           if(S = '0' and R = '0') then       -- Here if else statements to update the tmp variable. It can easily understand by Truth Table of SR Filp Flop
               tmp := tmp;
           elsif(S = '0' and R = '0') then
               tmp := 'Z';
           elsif(S = '0' and R = '0') then
               tmp := '0';
           else
               tmp := '1';
           end if;                                   -- end of second if statement  
       end if;                                       -- end of first if statement  
       Q <= tmp;                               -- Q and QBAR is updated from tmp variable
       QBAR <= not tmp;
   end PROCESS;                           -- End of the process  
end behaviooral;                       -- End of Architecture named "behaviooral"

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