Examine the Verilog HDL model of the clock_gen module that is shown below. Show
ID: 2268288 • Letter: E
Question
Examine the Verilog HDL model of the clock_gen module that is shown below. Show an equivalent desisn for this module that uses a single binary counter and some gating (and/or latching). Do t // This module generates the scan and debounce clocks pulses // that are derived from the 50 Mhz Input clock on the DE2-115 // board using clock division methods module clock_gen(cik in, scan_en, scan_clk, debounce_clk): input clk in, scan_en: output scan_cik, debounce_clk: reg (i6:01 count: assign scan clk = (scan en) ? count [16] : scan clk; assign debounceclk -count [121: always (posedge clk_in) begin countcount1: end endmodule For the clock_gen module above, given that the clk_in input is a 50 Mhz clock source what is the frequency of the scan clk and debounce clk signals that are produced? For the clock_gen module, how does the scan_en signal affect the scan_clk? How does it affect the debounce clk? Why do we need a debounce circuit in this design What factors should one consider when choosing the frequencies of clock_gen module out put clock signals? Would these values be appropriate for all mechanical push button nor mally open/monetarily closed devices? Why or why not?Explanation / Answer
1. frequency of scan_clk is 1/216 times of clk_in. Hence clk_in = 50Mhz then scan_clk = 763 hz
debounce_clk = 1/212 times of clk_in frequency. i.e. debounce_clk = 12.207khz
2. scan_clk toggles with 16th bit of count register only if scan_en signal is HIGH. There is no effect of scan_en on debounce_clk.
3. debounce circuits is used to eliminate the bouncing effect of mechanical switches used in the circuit. Any switch when turned ON / OFF toggles for few transitions before finally settling to a HIGH/LOW value. Hence its important to read the swich by the sequential circuit only after a certain delay introduced by the debouncing circuit.
4. Clock frequencies are selected in such a way that timing parameters like hold and setup time are not violated. Clock frequency should be easily divided by 2 n factors without introducing any fractions in the value. Else there is a scope of glitch in the circuit.
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.