Digital Electronics: Hello, Please answer clearly with detals as you can. Many T

Question

Digital Electronics:

Hello,

Please answer clearly with detals as you can.

Many Thanks for your help!

-What is a sensitivity list?

-How is a Johnson counter different from a Ring counter?

How to write behavioral code for various counters?

-What is a Mod counter, and what is its maximum count?

-How is an "instantiated project" different from an "all behavioral project?

-How would you describe a multiplexer using the conditional operator?

-What are the Verilog keywords used so far in digital electronics class?

-What is a logical component / primitive? name some of them...?

-What is "active-high" versus "active-low"?

-What are the main differences (concurrency/keywords/etc.) between Structural, Data Flow, and Behavioral Verilog?

-Why "AND" cannot be used in a sensitivity list between input names?

- how / when to use concatenation "{ }"?

-How would you describe a tri-stated device in data flow Verilog?

Explanation / Answer

SENSITIVITY LIST:-

The sensitivity list is a compact way of specifying the set of signals, events on which may resume a process. A sensitivity list is specified right after the keyword process. The sensitivity list is equivalent to the wait on statement, which is the last statement of the process statement section.

DIFFERENCE BETWEEN RING COUNTER AND JOHNSON COUNTER:-

Like a ring counter a Johnson counter is a shift register fed back on its' self. ... If the complement output of a ring counter is fed back to the input instead of the true output, a Johnson counter results. The difference between a ring counter and a Johnson counter is which output of the last stage is fed back (Q or Q').

MOD COUNTER:-
The number of different output states a counter can produce is called the modulo or modulus of the counter. The Modulus (or MOD-number) of a counter is the total number of unique states it passes through in one complete counting cycle with a mod-n counter being described also as a divide-by-n counter.

VERILOG KEY WORDS:-

always
and
assign
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force

LOGICAL COMPONENT:-

A logical component is an administrative entity which assigns logical systems, in the entire system landscape and across projects, to the following: a main instance of a product with a product version, e.g. the main instance CRM Server of the product SAP CRM with the product version 4.0.

ACTIVE HIGH VERSUS ACTIVE LOW:-

Simply put, this just describes how the pin is activated. If it's an active-low pin, you must “pull” that pin LOW by connecting it to ground. For an active high pin, you connect it to your HIGH voltage (usually 3.3V/5V). For example, let's say you have a shift register that has a chip enable pin, CE.

USE OF CONCETENATION:-

The word concatenate is just another way of saying "to combine" or "to join together". The CONCATENATE function allows you to combine text from different cells into one cell. In our example, we can use it to combine the text in column A and column B to create a combined name in a new column.

Related Questions

Navigate

• Browse (All)
• Browse D
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.