Digital Electronics: Please do not use C++ programming functions here because I

Question

Digital Electronics:

Please do not use C++ programming functions here because I am not allow to use it.

please write the code and compile it to make sure that it is correct and working.

Many thanks!

Design of a modulus 10 Up/Down Johnson Counter you will design and implement a modulus 10 Up/Down Johnson Counter with enable. The counter has an asynchronous reset input which brings the outputs to 0 as soon as the rst signal is asserted The counter counts on the negative edge of the clock. Develop the logic for this counter to be self-correcting. e.: If it comes up with a wrong count-correct itself.) The Up/Down Johnson counter has a clock input, CLK, count enable input, CEN, and an up/down control input, ULD. (Develop the function table with the priority being 1) CEN, 2) ULD. The counter has a 5-bit output, count, which outputs the current count as a 5-bit Johnson count. The value of the count will then be decoded in hexadecimal and displayed on the seven segment display. The Even-Odd counter operates as follows: When rst 1', the count should be reset to "00000 Otherwise, if the cen 1', on every clock cycle the counter should count up when ud '1' and count down when ud '0'. If cen '0' the counter holds ad the current value. Block diagram for the counter: CEN U D bit Johnson 5-bit Johnson to seven- Counter Segment decoder RST CLK D

Explanation / Answer

module mod1 (
input rst,
input CLK,
input CKE,
input U_D,
output reg [6:0] out1
);

reg [4:0] cur_state;
reg [4:0] next_state;
wire [4:0] Q;

parameter S0 = 5'b00000,
S1 = 5'b10000,
S2 = 5'b11000,
S3 = 5'b11100,
S4 = 5'b11110,
S5 = 5'b11111,
S6 = 5'b01111,
S7 = 5'b00111,
S8 = 5'b00011,
S9 = 5'b00001;


always @ (posedge CLK)
begin
if (rst)
cur_state <= S0;
else
cur_state <= next_state;
end

always @ (*) // here is the small modification
begin
if (rst)
next_state = S0;
else
begin

case(cur_state)
S0 : begin
if (U_D && CKE)
next_state = S1;
else if (!U_D && CKE)
next_state = S9;
else
next_state = S0;
end

S1 : begin
if (U_D && CKE)
next_state = S2;
else if (!U_D && CKE)
next_state = S0;
else
next_state = S1;
end

S2 : begin
if (U_D && CKE)
next_state = S3;
else if (!U_D && CKE)
next_state = S1;
else
next_state = S2;
end

S3 : begin
if (U_D && CKE)
next_state = S4;
else if (!U_D && CKE)
next_state = S2;
else
next_state = S3;
end


S4 : begin
if (U_D && CKE)
next_state = S5;
else if (!U_D && CKE)
next_state = S3;
else
next_state = S4;
end

S5 : begin
if (U_D && CKE)
next_state = S6;
else if (!U_D && CKE)
next_state = S4;
else
next_state = S5;
end

S6 : begin
if (U_D && CKE)
next_state = S7;
else if (!U_D && CKE)
next_state = S5;
else
next_state = S6;
end

S7 : begin
if (U_D && CKE)
next_state = S8;
else if (!U_D && CKE)
next_state = S6;
else
next_state = S7;
end

S8 : begin
if (U_D && CKE)
next_state = S9;
else if (!U_D && CKE)
next_state = S7;
else
next_state = S8;
end

S9 : begin
if (U_D)
next_state = S0;
else if (!U_D && CKE)
next_state = S8;
else
next_state = S9;
end

default : next_state = S0; // For self checking code i.e if goes to unwanted state
// It return to the S0 state
endcase
end

end


assign Q = cur_state;

always @(cur_state)
begin
case(cur_state)
S0 : out1 = 7'b111_1110; // represents 0
S1 : out1 = 7'b011_0000; // represents 1
S2 : out1 = 7'b110_1101; // represents 2
S3 : out1 = 7'b111_1001; // represents 3
S4 : out1 = 7'b011_0011; // represents 4
S5 : out1 = 7'b101_1011; // represents 5
S6 : out1 = 7'b101_1111; // represents 6
S7 : out1 = 7'b111_0000; // represents 7
S8 : out1 = 7'b111_1111; // represents 8
S9 : out1 = 7'b111_1011; // represents 9
endcase
end
endmodule

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