Digital Electronics: Please do not use C++ programming functions here because I

Question

Digital Electronics:

Please do not use C++ programming functions here because I am not allow to use it.

please write the code and compile it to make sure that it is correct and working.

Many thanks!

Design of a self-correcting Ring Counter this lab, you will design and implement a four-bit self-correcting ring counter. The inputs include the following signals: an asynchronous Reset "RST", ring right "RR", ring left "RL" and system clock "CLK". The "RST" initializes the counter to the 1000. The "Ring Right" sequence causes the following count sequence 1000-0100 0010 0001, while the "Ring Left" sequence causes the count sequence to be 1000 0001 0010 0100. When both RR and RL equal '1' the count will hold. The Asynchronous Reset "RST" causes the count to go to the initial state of 1000 Develop an al behavioral Verilog program to drive the four-bit self-correcting ring counter. Lab Procedure Implement and simulate this circuit using Quartus ll software as follows: 1. Create a new Quartus project. 2. Write a Verilog file that creates the four- bit self-correcting ring counter. 3. Compile your code and use the RTL Viewer to examine the implemented circuit. Verify that the synchronous ring counter is implemented correctly. 4. Create a Vector Waveform File (.vwf) which specifies the inputs and outputs of the circuit. Do a functional simulation to verify proper operation of the ring counter.

Explanation / Answer

The VERILOG code for the counter

// Design of self-correcting ring counter

' timescale 1ns/100ps

Module Counter ( RST , RR , RL , CLK , OUT );

input RST, RR , RL ,CLK ;

output OUT;

always@( posedge CLK or RST)

begin

  reg [2:0]A; ... three select lines needed

case1 (A=00) :

( RR==1 );

case2 (A=01):

(RL==1) ;

case3 (A=10):

(RL & RR == 1)

endcase

end

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