Write Verilog code to implement a positive-edge-triggered JK flip flop. timescal

Question

Write Verilog code to implement a positive-edge-triggered JK flip flop. timescale 1ns/100ps//time measurement unit is 1 nsec with 100 ps percision //Design a D flip flop //Author: Instructor This is of the Solved Question (To give an example of the expected criteria) for the next unsolved question module D_ff (clock, j, k, q): //defines the input and output into module input clock, j, k;//define input wire clock, j, k;//declare input type output q;//define output reg q;//declare output //Body of the design always @ (posedge clock) //executes following code at every clock rising edge begin q

Explanation / Answer

`timescale 1ns / 1ps    // time measurement unit is 1 nsec with 1ps precision

module SR_FF(clock,s,r,q); //defines input and ouput of flip flop
input clock,s,r;                   //define input
wire clock,s,r;                   //declare input type
output q;                          //define output
reg q;                               //declare output type
always @(posedge clock) //executes at every postive edge of clock
begin
q <= s | ((~r)&q);    // makes an assignment
end
endmodule

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