Write VHDL test bench model to simulate the Fibonacci Calculator model. This mod

Question

Write VHDL test bench model to simulate the Fibonacci Calculator model. This model, testbench model has no inputs, but declares and creates an instance the FibonacciCalculator Model and using two processes, one for generating the clock to the system and the other to apply values to the FibTermNum_H(4:0) and the Start_H signal VERIFIES that the FibonacciCalculator is computing the correct term values. You should exercise this test bench be asking it to calculate the following terms: Fib(0), Fib(10), Fib(20), Fib(30).

Explanation / Answer

module fib(input clock, reset, input [5:0] n, output reg ready, output [31:0] value)

reg [31:0] previous, current;
reg [5:0] counter;

// Reset the circuit
always @(posedge reset)
begin
previous <= 32'd0;
current <= 32'd1;
counter <= 32'd1;
end

// Compute next Fibonacci number
always @(posedge clock)
begin
// Increment current index
counter <= counter + 1;

// Efficient adders are automatically inferred
current <= current + previous;
previous <= current;

if (counter == n)
ready <= 1;
end

// Read the value of the nth fibonacci number from the internal register
assign value = current;

endmodule

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