Design a circuit that has two input ports: data (8-bit) and reset (1-bit) and tw

Question

Design a circuit that has two input ports: data (8-bit) and reset (1-bit) and two 8-bit output (W1 and W2). After a complete synchronous pulse on reset, in the next eight clocks, the circuit receives eight bytes of data on the data port on every rising edge of the clock. In the ninth clock, the result of the average of all received data bytes, and (LargestData + SmallestData)/2 become available on the output ports (W1, W2) of the circuit.

A. Implement this circuit using a mix of Verilog coding and Quartus II components. Design the datapath of this circuit using Quartus II components and design its controller with Verilog.

B. Run simulation to verify your design.

Kindly mention how this can be implemented and done. Right from circuit level with proper explanation.

Explanation / Answer

module My_module( reset, clock, data,w1,w2 );

input reset;
input clock;
input[7:0] data;
output[7:0]w1,w2;

reg[7:0] min,max,avg;
reg[7:0] bfr[7:0];
reg[3:0] cntr;
always @*
begin
    min = 8'b11111111;
max = 8'b00000000;
cntr = 4'b0000;
end

always @(posedge clock)
begin

bfr[cntr] = data;

if(data < min)
     min = data;
if(data > max)
max = data;

cntr = cntr + 1;
end
always @( cntr)
begin
if(cntr > 8)
{
cntr = 0;//4'b0000;
min = 8'b11111111;
max = 8'b00000000;
assign w1 = ( bfr[0] + bfr[1] + bfr[2] + bfr[3] +bfr[4] + bfr[5] + bfr[6] + bfr[7] ) >> 3; // Dividing by 8
avg = (max + min ) >> 1; //Dividing by 2
    assign w2 = avg;
}
end
endmodule

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