VHDL Problem: Create two vhdl files, based on the infromation given below for th
ID: 2248563 • Letter: V
Question
VHDL Problem:
Create two vhdl files, based on the infromation given below for the "Zero Pad" and "Sign Pad":
a) ZeroPad.vhd file which contains a VHDL description of a Zero pad circuit with an 8-bit input and a 32-bit output.
b) SignPad.vhd file which contains a VHDL description of a Sign pad circuit with an 8-bit input and a 32-bit output.
Zero Pad and Sign Pad
The function of the zero pad and the sign pad is to extend the size of their input. For this assignment an 8-bit signal is coming into the Zero Pad and Sign Pad. The output of these two blocks should be 32-bit. So, it is needed to pad the empty spaces on the output vector. The zero pad does this with 0’s and the sign pad does it with the MSB of the 8-bit input. This is depicted on figures 5 and 6.
Explanation / Answer
-- code for zero padding logic
library ieee;
use ieee.std_logic_1164.all;
entity zero_pad is
port (
in1 : in std_logic_vector(7 downto 0);
out1 : out std_logic_vector(31 downto 0)
);
end zero_pad;
architecure behav of zero_pad is
begin
process(in1)
begin
for i in 0 to 31 loop
if (i >= 0 and i <= 7) then
out1(i) <= in1(i);
else
out1(i) <= '0';
end loop;
end process;
end behav;
-- code for sign padding logic
library ieee;
use ieee.std_logic_1164.all;
entity sign_pad is
port (
in1 : in std_logic_vector(7 downto 0);
out1 : out std_logic_vector(31 downto 0)
);
end sign_pad;
architecure behav of sign_pad is
begin
process(in1)
begin
for i in 0 to 31 loop
if (i >= 0 and i <= 6) then
out1(i) <= in1(i);
else
if (in1(7) == 1'b1) then
out(i) <= '1' ;
else
out(i) <= '0';
end if;
end if ;
end process;
end behav;
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.