VHDL Problem: Create two vhdl files, based on the infromation given below for th
ID: 2248562 • Letter: V
Question
VHDL Problem:
Create two vhdl files, based on the infromation given below for the "Incrementer" and "Shifter":
a) Incrementer.vhd file which contains a VHDL description of the Incrementer
b) Shifter.vhd file which contains a VHDL description of the shifter explained below.
1. Incrementer
The function of the incrementer is as simple as adding 1 to the value at its output. This operation is performed only if the control signal inc = 1. If the control signal is 0 the output is the same as the input, no modification. The next figure show the diagram of the incrementer.
The input (Data_in) and the output (Data_out) are 32 bits each. The control signal (Inc) is 1bit.
2. Shifter
The shifter has two operations. It can either Shift Right Arithmetic (SRA) or it can Shift Left Logical (SLL).
The SRA1 is obtained by shifting all the bits to the right by 1 position. That means that the LSB is going to be lost. But the MSB is copied to keep the same size and the same sign of your binary number, see figure 2. The SRA1 is basically a division by 2.
The SLL8 is done in a similar manner as the SRA1 but with the difference of being done in the opposite direction (to the left) and instead of 1 position shifting is an 8 positions shift. Another difference is that the new available positions are fulfilled with 0’s, see figure below.
Figure 4 shows a diagram of the Shifter. It has a 32bit input/output port and 2 control signals SRA1 and SLL8. The Shifter works as follow:
• If SRA1 is asserted (equal to 1) you perform a Shift Right Arithmetic operation to the input and the result is assigned to the output.
• If SLL8 is asserted (equal to 1) you perform the Shift Left Logical operation to the input and the result is assigned to the output.
• If SRA1=0 and SLL8=0 the input goes straight to the output with no change. The same happens if both are asserted at the same time.
Explanation / Answer
-- code for Incrementer.vhd logic
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nncrementer is
port (
in1 : in std_logic_vector(31 downto 0);
out1 : out std_logic_vector(31 downto 0)
);
end incrementer;
architecure behav of incrementer is
signal temp : std_logic_vector(31 downto 0);
begin
temp <= (0 => '1', others => '0'); -- in short temp = 1
process(in1)
begin
out1 <= in1 + temp; -- increment the output by 1
end process;
end behav;
-- code for Shifter.vhd logic
library ieee;
use ieee.std_logic_1164.all;
entity shifter is
port (
in1 : in std_logic_vector(31 downto 0);
sra1 : in std_logic;
sll8 : in std_logic;
clk : in std_logic;
reset : in std_logic;
out1 : out std_logic_vector(31 downto 0)
);
end shifter;
architecure behav of shifter is
signal temp : std_logic_vector (31 downto 0);
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then -- when reset is applied then output = 0
temp <= (others => '0');
elsif (sra1 = '1') then -- when sra1 is applied then output is arithemetic shifted right by 1
temp <= in1(31) & in1(31 downto 1);
elsif (sll8 = '1') theN -- when sll8 is applied then output is logically shifted left by 8
for i in 0 to 31 loop
if (i <= 7) then
temp(i) <= '0';
else
temp(i) <= in1(i-8);
end if;
else
temp <= temp;
end if;
end if;
end process;
out1 <= temp; -- assign temp to output
end behav;
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