VHDL Problem: Create 32-Bit Tristate Output Register Use TransLatch.vhd and Mast
ID: 2248289 • Letter: V
Question
VHDL Problem: Create 32-Bit Tristate Output Register
Use TransLatch.vhd and MasterSlave.vhd ( Both are given below) to create:
- Reg32.vhd (A VHDL description of the 32-bit register with tristate output described above. Make the Clk input a rising-edge strobe. Implement the register as a component named “register_32”.). Simulate your design and make sure it generates the correct results.
Given:
A Tri-state buffer behaves like a regular buffer but it includes a third terminal called Enable. Whern enable is asserted (HIGH), the value at the output of the buffer is equal to the input value. The key difference is that when enable is negated (LOW), the output shows high impedance or a value of Z. The truth table of this buffer is shown below: Input EnableOutput 0 0 1 0 0 0 A 32bits Register with tri-state output is a collection of 32 flip flops. Similar to the register above, the 32bit Data_in bus is composed of 16 individual Data_in signals, one to each flip-flop. There is a single Clk signal controlling all the flip flops. A Reset signal is introduced to set the flip flop values to zero whenever it is asserted. The 32bit bus going into the buffer is a collection of all individual flip flop output signals. Data out will show the value that is stored on the register if and only if Enable is HIGH. This Register is shown below: 32 Bits-tri-state REGISTER Tri-state Buffer 132 32 32 Data in Data ou Clk Reset EnableExplanation / Answer
library ieee; use ieee.std_logic_1164.all; entity translatch is port (R:IN STD_LOGIC; D:IN STD_LOGIC; G:IN STD_LOGIC; Out_H: OUT STD_LOGIC; Out_L:OUT STD_LOGIC ); end translatch; architecture beh of translatch is BEGIN process(R,D,G) variable x:std_logic; begin if(R='0') then x:='0'; elsif (G='0') then x:=x; elsif (D='0') then x:='0'; else x:='1'; end if; Out_HRelated Questions
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