VHDL MODULE entity Lab4_JKFF_MODULE is Port ( J : in STD_LOGIC; K : in STD_LOGIC
ID: 1846096 • Letter: V
Question
VHDL MODULE
entity Lab4_JKFF_MODULE is Port ( J : in STD_LOGIC; K : in STD_LOGIC; CLK : in STD_LOGIC; Q : inout STD_LOGIC); end Lab4_JKFF_MODULE;
architecture Behavioral of Lab4_JKFF_MODULE is
begin process (J,K,CLK)
begin if (rising_edge (CLK)) then
if (J='0' and K='0') then Q <= Q; elsif (J='0' and K='1') then Q <='0'; elsif (J='1' and K='0') then Q <='1'; else Q <= not Q; end if; end if; end process; end Behavioral;
VHDL testbench
ENTITY Lab4_JKFF_TB_T IS END Lab4_JKFF_TB_T; ARCHITECTURE behavior OF Lab4_JKFF_TB_T IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Lab4_JKFF_MODULE PORT( J : IN std_logic; K : IN std_logic; CLK : IN std_logic; Q : INOUT std_logic ); END COMPONENT;
--Inputs signal J : std_logic := '0'; signal K : std_logic := '0'; signal CLK : std_logic := '0';
--BiDirs signal Q : std_logic;
-- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Lab4_JKFF_MODULE PORT MAP ( J => J, K => K, CLK => CLK, Q => Q );
-- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process;
stim_proc: process begin J<='1'; K<='0'; wait for CLK_period; J<='1'; K<='1'; wait for CLK_period; J<='1'; K<='1'; wait for CLK_period;
J<='1'; K<='1'; wait for CLK_period;
J<='0'; K<='0'; wait for CLK_period; WAIT;
end process;
END;
Hi, Im working on the given code of a jk flip flop. The codes I posted are working but now I have to modify it and add an ACTIVE LOW CLR signal. I know its not really a lot of modification but Im a little confused with the term active low. Can someone show me how to modify the module and the testbench? Or do I even have to modify the testbench? Also can someone explain to me what ACTIVE LOW exactly means? Does it mean I have to make the CLR signal like this: if CLR='1' then Q <='0'; or since it's active low it will be the other way around like this: if CLR='0' then Q <='0'; ?
Thanks!
VHDL MODULE
entity Lab4_JKFF_MODULE is Port ( J : in STD_LOGIC; K : in STD_LOGIC; CLK : in STD_LOGIC; Q : inout STD_LOGIC); end Lab4_JKFF_MODULE;
architecture Behavioral of Lab4_JKFF_MODULE is
begin process (J,K,CLK)
begin if (rising_edge (CLK)) then
if (J='0' and K='0') then Q <= Q; elsif (J='0' and K='1') then Q <='0'; elsif (J='1' and K='0') then Q <='1'; else Q <= not Q; end if; end if; end process; end Behavioral;
VHDL testbench
ENTITY Lab4_JKFF_TB_T IS END Lab4_JKFF_TB_T; ARCHITECTURE behavior OF Lab4_JKFF_TB_T IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Lab4_JKFF_MODULE PORT( J : IN std_logic; K : IN std_logic; CLK : IN std_logic; Q : INOUT std_logic ); END COMPONENT;
--Inputs signal J : std_logic := '0'; signal K : std_logic := '0'; signal CLK : std_logic := '0';
--BiDirs signal Q : std_logic;
-- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Lab4_JKFF_MODULE PORT MAP ( J => J, K => K, CLK => CLK, Q => Q );
-- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process;
stim_proc: process begin J<='1'; K<='0'; wait for CLK_period; J<='1'; K<='1'; wait for CLK_period; J<='1'; K<='1'; wait for CLK_period;
J<='1'; K<='1'; wait for CLK_period;
J<='0'; K<='0'; wait for CLK_period; WAIT;
end process;
END; ENTITY Lab4_JKFF_TB_T IS END Lab4_JKFF_TB_T; ARCHITECTURE behavior OF Lab4_JKFF_TB_T IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Lab4_JKFF_MODULE PORT( J : IN std_logic; K : IN std_logic; CLK : IN std_logic; Q : INOUT std_logic ); END COMPONENT;
--Inputs signal J : std_logic := '0'; signal K : std_logic := '0'; signal CLK : std_logic := '0';
--BiDirs signal Q : std_logic;
-- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Lab4_JKFF_MODULE PORT MAP ( J => J, K => K, CLK => CLK, Q => Q );
-- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process;
stim_proc: process begin J<='1'; K<='0'; wait for CLK_period; J<='1'; K<='1'; wait for CLK_period; J<='1'; K<='1'; wait for CLK_period;
J<='1'; K<='1'; wait for CLK_period;
J<='0'; K<='0'; wait for CLK_period; WAIT;
end process;
END;
Hi, Im working on the given code of a jk flip flop. The codes I posted are working but now I have to modify it and add an ACTIVE LOW CLR signal. I know its not really a lot of modification but Im a little confused with the term active low. Can someone show me how to modify the module and the testbench? Or do I even have to modify the testbench? Also can someone explain to me what ACTIVE LOW exactly means? Does it mean I have to make the CLR signal like this: if CLR='1' then Q <='0'; or since it's active low it will be the other way around like this: if CLR='0' then Q <='0'; ?
Thanks!
Explanation / Answer
Active low means that when you provide a low,i.e,0 signal to that variable ,it will perform the function.In this case,CLR is an active low signal which means that when CLR is low,i.e,0,then the output is cleared or in other terms becomes zero.When it is high,the CLR function is not performed.
In order to modify the module and testbench,yo have to include an input port named CLR .Also when you define it as an input,put the initial value as 1 or else evrything will be cleared!.You can add its functionality in the beginning of the functional block like if CLR is 0,then Q<='0'.All the best!
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