VHDL Code for PIR based Security Alert System using FPGA? Solution library IEEE;

Question

VHDL Code for PIR based Security Alert System using FPGA?

Explanation / Answer

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity pir is port( clock: in std_logic; din : in std_logic; op1 : out std_logic ; op2 : out std_logic ; op3 : out std_logic ; op4 : out std_logic ; buz : out std_logic:='0'; pir:in std_logic; led:out std_logic:='0'; txd: out std_logic); end entity pir; architecture rtl of test is type state1 is (ready1,b01,b02,b03); signal ps1 : state1 := ready1; type state is (ready,b0); signal ps : state := ready; signal start,stop : std_logic; signal store : std_logic_vector(7 downto 0) := "10101010"; constant system_speed: natural := 50e6; signal baudrate_clock, second_clock, old_second_clock: std_logic; signal bit_counter: unsigned(3 downto 0) := x"9"; signal shift_register: unsigned(9 downto 0) := (others => '0'); signal char_index: natural range 0 to 99; component clock_generator generic(clock_in_speed, clock_out_speed: integer); port( clock_in: in std_logic; clock_out: out std_logic); end component; begin baudrate_generator: clock_generator generic map(clock_in_speed => system_speed, clock_out_speed => 9600) port map( clock_in => clock, clock_out => baudrate_clock); second_generator: clock_generator generic map(clock_in_speed => system_speed, clock_out_speed => 1) port map( clock_in => clock, clock_out => second_clock); send: process(baudrate_clock) begin if baudrate_clock'event and baudrate_clock = '1' then led shift_register shift_register shift_register shift_register shift_register

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