please help 8. A set of control signals is listed below. Given our design of the
ID: 2266357 • Letter: P
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please help
8. A set of control signals is listed below. Given our design of the Relatively Simple CPU (reterence Figures 6.15 and 6.16), identify which of these control signals are used in completing the LDAC instruction (specifically LDAC 05551). Besides identification, you should list them in a valid order of execution from earliest to latest. In all descriptions, "bus" refers to the internal bus of the CPU shown in Figure 6.15. Note that not every the necessary signal will be listed. Note also that not all control signals listed below are relevant pleting the LDAC operation. Control signals that can be issued simultaneously do no have to be identified as such---placing them in any correct sequential order is sufficient. You may assume that the CPU has completed the fetch cycle and that the opcode for LDAC is stored in IR (i.e. the next execution state to occur is LDACI). (15 points) a. Enable writing of data into memory. b. Enable DR to put its value (the high order address bits, 05H) onto bus. c. Enable AR to load the address of the memory cell (0555H) from the bus. d. Enable memory to load the data stored in memory cell 058Sti onto the bus. e. Enable DR to put its value (the low order address bits, 55H) on the bus. f. Enable R to put its value on the bus. g. h. i. Enable TR to put its value on the bus Enable AC to put its value on the bus. Enable TR to load the value from DR. Enable AC to load the value from the ALU. j.Explanation / Answer
In reordering the instructions in the correct order,we get
a)Enable R to put its value on the bus.
b)Enable DR to put its value(the low order address bits 55H ) on the bus.
c)Enable TR to load the value from DR.
d)Enable DR to put its value(the high order address bits 05H) onto bus.
e)Enable TR to put its value on bus.
f)Enable writing of data into memory.
g)Enable AR to load the address of the memory cell(0555H) from the bus.
h)Enable memory to load the data stored in memory cell 0555H onto the bus.
i)Enable AC to load value from the ALU.
j)Enable AC to put its value on the bus.
Describing the sequence of instructions in detail,
Initially the bits are stored in any register R which is loaded into the internal bus. From the registers, first the lower order bits are sent to DR register. Then in order to take the higher order bits into DR register,the lower order bits are sent to temporary register TR so that the bits do not overlap each other. After sending the lower order bits to TR, the higher order bits are sent to DR.Now the values in TR are put on the internal bus for operation. Now the writing of data is enabled in the memory and the value in AR is loaded with address of memory cell 0555H. Then the operation is performed in the ALU and the result is stored in AC or accumulator and then it is loaded into the bus.
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