ECE 501, Fa17 Final Exam, Decemb401 Veu are allow two standa ard size Page 5 of

Question

ECE 501, Fa17 Final Exam, Decemb401 Veu are allow two standa ard size Page 5 of 6 theets (8.5 x 11 inches) with notes on both sides. No electrorics including computers using the 3 bit LFSR code below til starting with the seed value. (20 points) in the simulation graph with the binary values for the first four output values of A graph with code represent? iibeary sece: use seeestd logic 1164.a1 entsty LESR 3bit s port ( .out downto ) ;-- out put sta-logic-vector, :in std 1ogie in std logie :in std logie t2 eonting enable clock reset Input clock Isput reset end entity LESR 3bie architecture beh of LFSR 3bit ia ignal A count std logie vector (2 donto aignal feedback std logier teedback A countto) xor Acount (2) procesa (clock, reset) begin begin a count*111 then els (ning-edge (elock)) if (enable-'then a count )eedback A count(i)

Explanation / Answer

Its a Fibonacci LFSR

1

1

1

0

1

1

1

0

1

0

1

0

Seed Value

2nd Value

3rd Value

4th Value

1

1

1

0

1

1

1

0

1

0

1

0

Seed Value

2nd Value

3rd Value

4th Value

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