HI! Can you help me to write a testbench code for a \"T flipflop using D flipflo

Question

HI! Can you help me to write a testbench code for a "T flipflop using D flipflop" VHDL program.

Here is how the task sounds.

I have my T flipflop VDHL implementation here:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity t_flip_flop is

Port ( T : in STD_LOGIC;
Q : inout STD_LOGIC;
QN : inout STD_LOGIC);
end t_flip_flop;

architecture t_flip_flop_arch of t_flip_flop is

   component d_flip_flop is
       Port (    D : in STD_LOGIC;
                   CLK : in STD_LOGIC;
                   Q : inout STD_LOGIC;
                   QN : inout STD_LOGIC);
   end component;
  
   signal T_Q_XOR: STD_LOGIC;
   signal CLK: STD_LOGIC;
      
begin
   T_Q_XOR <= T xor Q;
   U0: d_flip_flop port map (T_Q_XOR, CLK, Q, QN);

end t_flip_flop_arch;

And this is my D flipflop with a testbench:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity d_flip_flop is

Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : inout STD_LOGIC;
QN : inout STD_LOGIC);
end d_flip_flop;

architecture d_flip_flop_arch of d_flip_flop is
   component d_latch is       
           Port ( C : in STD_LOGIC;
                   D : in STD_LOGIC;
                   Q : inout STD_LOGIC;
                   QN : inout STD_LOGIC);   
   end component;      

signal CLKN: STD_LOGIC;   
signal QM: STD_LOGIC;
      
begin    
   U1: d_latch port map (CLKN, D, QM);   
   U2: d_latch port map (CLK, QM, Q, QN);      
   CLKN <= not CLK;   

end d_flip_flop_arch;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d_flip_flop_testbench IS

END d_flip_flop_testbench;

ARCHITECTURE behavior OF d_flip_flop_testbench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT d_flip_flop
PORT(
D : IN std_logic;
CLK : IN std_logic;
Q : INOUT std_logic;
QN : INOUT std_logic
);
END COMPONENT;
--Inputs

signal D : std_logic := '0';
signal CLK : std_logic := '0';

   --BiDirs
signal Q : std_logic;
signal QN : std_logic;

-- Clock period definitions
constant CLK_period : time := 10 ns;

BEGIN

   -- Instantiate the Unit Under Test (UUT)
uut: d_flip_flop PORT MAP (
D => D,
CLK => CLK,
Q => Q,
QN => QN
);

-- Clock process definitions
CLK_process :process
begin
       CLK <= '0';
       wait for CLK_period/2;
       CLK <= '1';
       wait for CLK_period/2;
end process;
-- Stimulus process

d_flip_flop_testbench : process
   begin      
   wait for 20 ns;       
   d <= '0';       
   wait for CLK_period*2;       
   d <= '1';       
   wait for CLK_period*2;       
   d <= '0';       
   wait for CLK_period*2;       
   d <= '1';       
   wait for CLK_period*2;
   wait;
   end process;

END;

Explanation / Answer

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t_flip_flop_testbench IS

END t_flip_flop_testbench;

ARCHITECTURE behavior OF t_flip_flop_testbench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT t_flip_flop
PORT(
T : IN std_logic;
CLK : IN std_logic;
Q : INOUT std_logic;
QN : INOUT std_logic
);
END COMPONENT;
--Inputs

signal T : std_logic := '0';
signal CLK : std_logic := '0';

   --BiDirs
signal Q : std_logic;
signal QN : std_logic;

-- Clock period definitions
constant CLK_period : time := 10 ns;

BEGIN

   -- Instantiate the Unit Under Test (UUT)
uut: t_flip_flop PORT MAP (
T => T,
CLK => CLK,
Q => Q,
QN => QN
);

-- Clock process definitions
CLK_process :process
begin
       CLK <= '0';
       wait for CLK_period/2;
       CLK <= '1';
       wait for CLK_period/2;
end process;
-- Stimulus process

t_flip_flop_testbench : process
   begin      
   wait for 20 ns;       
T <= '0';       
   wait for CLK_period*2;       
T <= '1';       
   wait for CLK_period*2;       
T <= '0';       
   wait for CLK_period*2;       
T <= '1';       
   wait for CLK_period*2;
   wait;
   end process;

END;

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