How can I implement an ALU of 4 Bits with the functions giving above? How can im
ID: 2266594 • Letter: H
Question
How can I implement an ALU of 4 Bits with the functions giving above?
How can implement it only using Different Logic Gates and NOT a Mux ?
It would be of really good help if it can be show on Logicsim
Inputs Function Table S2 St So Operation Comments Outputs CLEAR B minus A A minus B Needs ON-1 Needs CN-0 Exclusive-OR OR AND F3F2F1Fo = 1111 0 1 Aplus B 74LS382 74HC382 A+B AB PRESET B, CN Notes: S inputs select operation. OVR= 1 for signed-number overflow OVR ALU A = 4-bit input number B = 4-bit input number F = 4-bit output number CN carry out of MSB position OVR overflow indicator CN carry into LSB position s= 3-bit operation select inputsExplanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
Port ( inp_a : in signed(3 downto 0);
inp_b : in signed(3 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
out_alu : out signed(3 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(inp_a, inp_b, sel)
begin
case sel is
when "000" =>
out_alu<= inp_a + inp_b; --addition
when "001" =>
out_alu<= inp_a - inp_b; --subtraction
when "010" =>
out_alu<= inp_a - 1; --sub 1
when "011" =>
out_alu<= inp_a + 1; --add 1
when "100" =>
out_alu<= inp_a and inp_b; --AND gate
when "101" =>
out_alu<= inp_a or inp_b; --OR gate
when "110" =>
out_alu<= not inp_a ; --NOT gate
when "111" =>
out_alu<= inp_a xor inp_b; --XOR gate
when others =>
NULL;
end case;
end process;
end Behavioral;
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