Design a synchronized counter with a 7 segment counter that passes through the s

Question

Design a synchronized counter with a 7 segment counter that passes through the sequence of the numbers 82567 and then repeat it. The design should be the most economical possible. That is, it must require fewer possible logic gates, fewer entries to the Logic gates, less quantity of integrated circuits (ICs) to implement it Also consider using NOR and NAND gates. It is recommended to design for each type of flip flop (D, JK and / or T) and determine which provides a more efficient circuit (more economical, less delay, logic gates with less tickets, etc.).

Each segment will be activated independently. Do not use a commercial decoder for the "7 segment". Should design the circuit that will feed each counter entrance.

Simulation: • Simulate with the Logisim program. This will allow you to confirm that your design is correct. You must see that the sequence is fulfilled according to what look at the 7-segment counter. • Simulate with Pspice to obtain the time diagram. For this diagram you will also corroborate the operation of the circuit

Explanation / Answer

The latch or flip flop circuit which respond to their inputs only if their enable input(E) held at an active high or low levels called level trigerred latched or flip flops

Positive level troggred and Negative level triggred

D latch is simple SR latch with NAND inverter connected between its S and R inputs

due to NAND inverter S and R always be the complements of each other

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