In the following VHDL process A , B , C , and D are all integers that have a val

Q: In the following VHDL process A , B , C , and D are all integers that have a val

In p2 Process E signal is in sensitive list. All the assingment in this block is blocking type by means the assgnment are done in sequential manner. Let say at t = 20 ns Signal E changes '0' to '1' than at t = 20 + 5 = 25 ns A = '1' B = '2' at t = 35 ns C = '2' at t = 38 ns D = '2' at t = 53 ns A = '6' and B = '9'

ID: 2267344 • Letter: I

Question

In the following VHDL process A, B, C, and D are all integers that have a value of 0 at time 10 ns. If E changes from ‘0’ to ‘1’ at time 20 ns, specify the time(s) at which each signal will change and the value to which it will change. List these changes in chronological order (20, 20 , 20 2 , etc.).

p2: process(E) begin

A <= 1 after 5 ns; B <= A + 1;
C <= B after 10 ns;

D <= B after 3 ns;
A <= A + 5 after 15 ns; B <= B + 7;

end process p2;

PLEASE GIVE DETAILED EXPLANATIONS OF EACH STEP

Explanation / Answer

In p2 Process E signal is in sensitive list.

All the assingment in this block is blocking type by means the assgnment are done in sequential manner.

Let say at t = 20 ns Signal E changes '0' to '1' than

at t = 20 + 5 = 25 ns A = '1' B = '2'

at t = 35 ns C = '2'

at t = 38 ns D = '2'

at t = 53 ns A = '6' and B = '9'

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In the following VHDL process A , B , C , and D are all integers that have a val

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