Design a “rgb2grascale” converter using a combinational circuit. Basically, the
ID: 2268351 • Letter: D
Question
Design a “rgb2grascale” converter using a combinational circuit. Basically, the grayscale image is obtained from the RGB image by combining 30% of RED, 60% of GREEN and 11% of BLUE. More specifically, each 8-bit grayscale pixel can be calculated as 0.2989 * R + 0.5870 * G + 0.1140 * B where R, G, and B are 8-bit red, green, and blue pixels, respectively. The resulting image will be two dimensional. The value 0 represents black and the value 255 represents white. The range will be between black and white values.
First of all, finish the design and simulation (complete the vhdl codes given step 1-5 ) . Please show the design, transcript result, and the simulation waveform.
partial code included .vhd and testbench code:
--------------------------------------------------------------------------------------------------//
----------- module: rgb2gs_cmb: rgb2gsayscale combinational circuit design ---------------------//
----------- author: DR. X ----------------------------------------------------------------------//
----------- date: 01/10/2018 ----------------------------------------------------------------//
----------- version: 2.0 ----------------------------------------------------------------//
--------------------------------------------------------------------------------------------------//
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; --used by arithmatic calculation for std_logic_vector
entity rgb2gs_cmb is
Port ( rst : in std_logic ;
r2g_en : in std_logic ;
r : in std_logic_vector(7 downto 0);
g : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
gs : out std_logic_vector(7 downto 0));
end rgb2gs_cmb;
architecture Behavioral of rgb2gs_cmb is
signal r1, r2, r3, r38 : std_logic_vector(15 downto 0);
signal g1, g2, g3, g4, g75 : std_logic_vector(15 downto 0);
signal b1, b2, b3, b4, b15 : std_logic_vector(15 downto 0);
signal gs16bit : std_logic_vector(15 downto 0);
begin
-----------------------------------------------------
---------------- rx38 -------------------------------
-- Hint: 38*r=(32+4+2)*r=2^5*r+2^2*r+2*r ------------
-----------------------------------------------------
r1 <= ("000" & r & "00000");
r2 <= ("000000" & r & "00");
r3 <= ("0000000" & r & "0");
r38 <= x"0000" when (rst = '0') else
(r1 + r2 + r3) when (r2g_en = '1') else
r38;
-----------------------------------------------------
-- Step 1: Please design gx75 -----------------------
-- Hint: 75*g=(64+8+2+1)*g=2^6*g+2^3*g+2*g+g --------
-----------------------------------------------------
-----------------------------------------------------
-- Step 2: Please design bx15 -----------------------
-- Hint: 15*b=(8+4+2+1)*b=2^3*b+2^2*b+2*b+b --------
-----------------------------------------------------
-----------------------------------------------------
-- Step 3: Please add gs16bit=r38+g75+b15------------
-----------------------------------------------------
-----------------------------------------------------
-- Step 4: Please design gs16bit/128 ----------------
-- Hint: move the lower 7 bits out and --------------
-- keep the higher 8 bits as the output of gs -------
-----------------------------------------------------
end Behavioral;
--------------------------------------------------------------------------------------------------//
----------- module: rgb2gs_cmb: rgb2gsayscale combinational circuit tb------------- -------------//
----------- author: DR. X ----------------------------------------------------------------------//
----------- date: 01/10/2018 ----------------------------------------------------------------//
----------- version: 2.0 ----------------------------------------------------------------//
--------------------------------------------------------------------------------------------------//
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rgb2gs_cmb_tb is
end rgb2gs_cmb_tb;
architecture tb of rgb2gs_cmb_tb is
---------------------------------------
------component of dut-----------------
---------------------------------------
component rgb2gs_cmb is
Port ( rst : in std_logic ;
r2g_en : in std_logic ;
r : in std_logic_vector(7 downto 0);
g : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
gs : out std_logic_vector(7 downto 0));
end component;
---------------------------------------
------wire declaration----------------
---------------------------------------
signal rst : std_logic ;
signal r2g_en : std_logic ;
signal r : std_logic_vector(7 downto 0);
signal g : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
signal gs : std_logic_vector(7 downto 0);
begin
------------------------------------------------------------------------
------Step 5: Please instantiate the dut and connect the ports ---------
------------------------------------------------------------------------
u_rgb2gs_cmb: rgb2gs_cmb
port map(rst => ,
r2g_en => ,
r => ,
g => ,
b => ,
gs => );
-------------------------------------------------
------clock and reset generator: 50MHz ----------
-------------------------------------------------
rst_proc: rst <= '0', '1' after 20 ns;
-------------------------------------------------
------------- rgb2gs enable ------------------
-------------------------------------------------
r2g_en_proc: r2g_en <= '0', '1' after 20 ns, '0' after 220 ns;
---------------------------------------
------input model: r ------------------
---------------------------------------
stim_proc: process
begin
r <= x"00";
g <= x"00";
b <= x"00";
wait for 20 ns;
r <= x"b0";
g <= x"a7";
b <= x"98";
wait for 20 ns;
r <= x"b2";
g <= x"aa";
b <= x"9d";
wait for 20 ns;
r <= x"a9";
g <= x"a9";
b <= x"9d";
wait for 20 ns;
r <= x"ab";
g <= x"a2";
b <= x"91";
wait for 20 ns;
r <= x"a3";
g <= x"9c";
b <= x"96";
wait for 20 ns;
r <= x"7b";
g <= x"74";
b <= x"6a";
wait for 20 ns;
r <= x"89";
g <= x"5e";
b <= x"3b";
wait for 20 ns;
r <= x"b3";
g <= x"6e";
b <= x"47";
wait for 20 ns;
r <= x"af";
g <= x"70";
b <= x"45";
wait for 20 ns;
r <= x"ba";
g <= x"7a";
b <= x"4c";
wait for 100 ns;
wait;
end process;
---------------------------------------
--------monitor -----------------------
---------------------------------------
monitor_proc: process
begin
report "======== Please check the results of waveform and transcript / Author: Dr. XY, 01/10/2018 =======" ;
wait for 30 ns;
if(gs=x"a7") then
report "1st Pixel RIGHT, the DUT output gs is a7" ;
else
report "1st Pixel ERROR: expected gs is a7" ;
report "1st Pixel rx38 ERROR: expected r38 is 1a20" ;
report "1st Pixel gx75 ERROR: expected r38 is 30ed" ;
report "1st Pixel bx15 ERROR: expected r38 is 08e8" ;
end if;
wait for 20 ns;
if(gs=x"aa") then
report "2nd Pixel RIGHT, the DUT output gs is aa" ;
else
report "2nd Pixel ERROR: expected gs is aa" ;
report "2nd Pixel rx38 ERROR: expected r38 is 1a6c" ;
report "2nd Pixel gx75 ERROR: expected r38 is 31ce" ;
report "2nd Pixel bx15 ERROR: expected r38 is 0933" ;
end if;
wait for 20 ns;
if(gs=x"a7") then
report "3rd Pixel RIGHT, the DUT output gs is a7" ;
else
report "3rd Pixel ERROR: expected gs is a7" ;
report "3rd Pixel rx38 ERROR: expected r38 is 1916" ;
report "3rd Pixel gx75 ERROR: expected r38 is 3183" ;
report "3rd Pixel bx15 ERROR: expected r38 is 0933" ;
end if;
wait for 20 ns;
if(gs=x"a2") then
report "4th Pixel RIGHT, the DUT output gs is a2" ;
else
report "4th Pixel ERROR: expected gs is a2" ;
report "4th Pixel rx38 ERROR: expected r38 is 1962" ;
report "4th Pixel gx75 ERROR: expected r38 is 2f76" ;
report "4th Pixel bx15 ERROR: expected r38 is 087f" ;
end if;
wait for 20 ns;
if(gs=x"9d") then
report "5th Pixel RIGHT, the DUT output gs is 9d" ;
else
report "5th Pixel ERROR: expected gs is 9d" ;
report "5th Pixel rx38 ERROR: expected r38 is 1832" ;
report "5th Pixel gx75 ERROR: expected r38 is 2cb4" ;
report "5th Pixel bx15 ERROR: expected r38 is 08ca" ;
end if;
wait for 20 ns;
if(gs=x"74") then
report "6th Pixel RIGHT, the DUT output gs is 74" ;
else
report "6th Pixel ERROR: expected gs is 74" ;
report "6th Pixel rx38 ERROR: expected r38 is 1242" ;
report "6th Pixel gx75 ERROR: expected r38 is 21fc" ;
report "6th Pixel bx15 ERROR: expected r38 is 0636" ;
end if;
wait for 20 ns;
if(gs=x"66") then
report "7th Pixel RIGHT, the DUT output gs is 66" ;
else
report "7th Pixel ERROR: expected gs is 66" ;
report "7th Pixel rx38 ERROR: expected r38 is 1456" ;
report "7th Pixel gx75 ERROR: expected r38 is 1b8a" ;
report "7th Pixel bx15 ERROR: expected r38 is 0375" ;
end if;
wait for 20 ns;
if(gs=x"7d") then
report "8th Pixel RIGHT, the DUT output gs is 7d" ;
else
report "8th Pixel ERROR: expected gs is 7d" ;
report "8th Pixel rx38 ERROR: expected r38 is 1a92" ;
report "8th Pixel gx75 ERROR: expected r38 is 203a" ;
report "8th Pixel bx15 ERROR: expected r38 is 0429" ;
end if;
wait for 20 ns;
if(gs=x"7d") then
report "9th Pixel RIGHT, the DUT output gs is 7d" ;
else
report "9th Pixel ERROR: expected gs is 7d" ;
report "9th Pixel rx38 ERROR: expected r38 is 19fa" ;
report "9th Pixel gx75 ERROR: expected r38 is 20d0" ;
report "9th Pixel bx15 ERROR: expected r38 is 040b" ;
end if;
wait for 20 ns;
if(gs=x"87") then
report "10th Pixel RIGHT, the DUT output gs is 87" ;
else
report "10th Pixel ERROR: expected gs is 85" ;
report "10th Pixel rx38 ERROR: expected r38 is 1b9c" ;
report "10th Pixel gx75 ERROR: expected r38 is 23be" ;
report "10th Pixel bx15 ERROR: expected r38 is 0474" ;
end if;
wait for 100 ns;
wait ;
end process;
end tb;
Explanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; --used by arithmatic calculation for std_logic_vector
entity rgb2gs_cmb is
Port ( rst : in std_logic ;
r2g_en : in std_logic ;
r : in std_logic_vector(7 downto 0);
g : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
gs : out std_logic_vector(7 downto 0));
end rgb2gs_cmb;
architecture Behavioral of rgb2gs_cmb is
signal r1, r2, r3, r38 : std_logic_vector(15 downto 0);
signal g1, g2, g3, g4, g75 : std_logic_vector(15 downto 0);
signal b1, b2, b3, b4, b15 : std_logic_vector(15 downto 0);
signal gs16bit : std_logic_vector(15 downto 0);
begin
-----------------------------------------------------
---------------- rx38 -------------------------------
-- Hint: 38*r=(32+4+2)*r=2^5*r+2^2*r+2*r ------------
-----------------------------------------------------
r1 <= ("000" & r & "00000");
r2 <= ("000000" & r & "00");
r3 <= ("0000000" & r & "0");
r38 <= x"0000" when (rst = '0') else
(r1 + r2 + r3) when (r2g_en = '1') else
r38;
-----------------------------------------------------
-- Step 1: Please design gx75 -----------------------
-- Hint: 75*g=(64+8+2+1)*g=2^6*g+2^3*g+2*g+g --------
-----------------------------------------------------
-----------------------------------------------------
-- Step 2: Please design bx15 -----------------------
-- Hint: 15*b=(8+4+2+1)*b=2^3*b+2^2*b+2*b+b --------
-----------------------------------------------------
-----------------------------------------------------
-- Step 3: Please add gs16bit=r38+g75+b15------------
-----------------------------------------------------
-----------------------------------------------------
-- Step 4: Please design gs16bit/128 ----------------
-- Hint: move the lower 7 bits out and --------------
-- keep the higher 8 bits as the output of gs -------
-----------------------------------------------------
end Behavioral;
--------------------------------------------------------------------------------------------------//
----------- module: rgb2gs_cmb: rgb2gsayscale combinational circuit tb------------- -------------//
----------- author: DR. X ----------------------------------------------------------------------//
----------- date: 01/10/2018 ----------------------------------------------------------------//
----------- version: 2.0 ----------------------------------------------------------------//
--------------------------------------------------------------------------------------------------//
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rgb2gs_cmb_tb is
end rgb2gs_cmb_tb;
architecture tb of rgb2gs_cmb_tb is
---------------------------------------
------component of dut-----------------
---------------------------------------
component rgb2gs_cmb is
Port ( rst : in std_logic ;
r2g_en : in std_logic ;
r : in std_logic_vector(7 downto 0);
g : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
gs : out std_logic_vector(7 downto 0));
end component;
---------------------------------------
------wire declaration----------------
---------------------------------------
signal rst : std_logic ;
signal r2g_en : std_logic ;
signal r : std_logic_vector(7 downto 0);
signal g : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
signal gs : std_logic_vector(7 downto 0);
begin
------------------------------------------------------------------------
------Step 5: Please instantiate the dut and connect the ports ---------
------------------------------------------------------------------------
u_rgb2gs_cmb: rgb2gs_cmb
port map(rst => ,
r2g_en => ,
r => ,
g => ,
b => ,
gs => );
-------------------------------------------------
------clock and reset generator: 50MHz ----------
-------------------------------------------------
rst_proc: rst <= '0', '1' after 20 ns;
-------------------------------------------------
------------- rgb2gs enable ------------------
-------------------------------------------------
r2g_en_proc: r2g_en <= '0', '1' after 20 ns, '0' after 220 ns;
---------------------------------------
------input model: r ------------------
---------------------------------------
stim_proc: process
begin
r <= x"00";
g <= x"00";
b <= x"00";
wait for 20 ns;
r <= x"b0";
g <= x"a7";
b <= x"98";
wait for 20 ns;
r <= x"b2";
g <= x"aa";
b <= x"9d";
wait for 20 ns;
r <= x"a9";
g <= x"a9";
b <= x"9d";
wait for 20 ns;
r <= x"ab";
g <= x"a2";
b <= x"91";
wait for 20 ns;
r <= x"a3";
g <= x"9c";
b <= x"96";
wait for 20 ns;
r <= x"7b";
g <= x"74";
b <= x"6a";
wait for 20 ns;
r <= x"89";
g <= x"5e";
b <= x"3b";
wait for 20 ns;
r <= x"b3";
g <= x"6e";
b <= x"47";
wait for 20 ns;
r <= x"af";
g <= x"70";
b <= x"45";
wait for 20 ns;
r <= x"ba";
g <= x"7a";
b <= x"4c";
wait for 100 ns;
wait;
end process;
---------------------------------------
--------monitor -----------------------
---------------------------------------
monitor_proc: process
begin
report "======== Please check the results of waveform and transcript / Author: Dr. XY, 01/10/2018 =======" ;
wait for 30 ns;
if(gs=x"a7") then
report "1st Pixel RIGHT, the DUT output gs is a7" ;
else
report "1st Pixel ERROR: expected gs is a7" ;
report "1st Pixel rx38 ERROR: expected r38 is 1a20" ;
report "1st Pixel gx75 ERROR: expected r38 is 30ed" ;
report "1st Pixel bx15 ERROR: expected r38 is 08e8" ;
end if;
wait for 20 ns;
if(gs=x"aa") then
report "2nd Pixel RIGHT, the DUT output gs is aa" ;
else
report "2nd Pixel ERROR: expected gs is aa" ;
report "2nd Pixel rx38 ERROR: expected r38 is 1a6c" ;
report "2nd Pixel gx75 ERROR: expected r38 is 31ce" ;
report "2nd Pixel bx15 ERROR: expected r38 is 0933" ;
end if;
wait for 20 ns;
if(gs=x"a7") then
report "3rd Pixel RIGHT, the DUT output gs is a7" ;
else
report "3rd Pixel ERROR: expected gs is a7" ;
report "3rd Pixel rx38 ERROR: expected r38 is 1916" ;
report "3rd Pixel gx75 ERROR: expected r38 is 3183" ;
report "3rd Pixel bx15 ERROR: expected r38 is 0933" ;
end if;
wait for 20 ns;
if(gs=x"a2") then
report "4th Pixel RIGHT, the DUT output gs is a2" ;
else
report "4th Pixel ERROR: expected gs is a2" ;
report "4th Pixel rx38 ERROR: expected r38 is 1962" ;
report "4th Pixel gx75 ERROR: expected r38 is 2f76" ;
report "4th Pixel bx15 ERROR: expected r38 is 087f" ;
end if;
wait for 20 ns;
if(gs=x"9d") then
report "5th Pixel RIGHT, the DUT output gs is 9d" ;
else
report "5th Pixel ERROR: expected gs is 9d" ;
report "5th Pixel rx38 ERROR: expected r38 is 1832" ;
report "5th Pixel gx75 ERROR: expected r38 is 2cb4" ;
report "5th Pixel bx15 ERROR: expected r38 is 08ca" ;
end if;
wait for 20 ns;
if(gs=x"74") then
report "6th Pixel RIGHT, the DUT output gs is 74" ;
else
report "6th Pixel ERROR: expected gs is 74" ;
report "6th Pixel rx38 ERROR: expected r38 is 1242" ;
report "6th Pixel gx75 ERROR: expected r38 is 21fc" ;
report "6th Pixel bx15 ERROR: expected r38 is 0636" ;
end if;
wait for 20 ns;
if(gs=x"66") then
report "7th Pixel RIGHT, the DUT output gs is 66" ;
else
report "7th Pixel ERROR: expected gs is 66" ;
report "7th Pixel rx38 ERROR: expected r38 is 1456" ;
report "7th Pixel gx75 ERROR: expected r38 is 1b8a" ;
report "7th Pixel bx15 ERROR: expected r38 is 0375" ;
end if;
wait for 20 ns;
if(gs=x"7d") then
report "8th Pixel RIGHT, the DUT output gs is 7d" ;
else
report "8th Pixel ERROR: expected gs is 7d" ;
report "8th Pixel rx38 ERROR: expected r38 is 1a92" ;
report "8th Pixel gx75 ERROR: expected r38 is 203a" ;
report "8th Pixel bx15 ERROR: expected r38 is 0429" ;
end if;
wait for 20 ns;
if(gs=x"7d") then
report "9th Pixel RIGHT, the DUT output gs is 7d" ;
else
report "9th Pixel ERROR: expected gs is 7d" ;
report "9th Pixel rx38 ERROR: expected r38 is 19fa" ;
report "9th Pixel gx75 ERROR: expected r38 is 20d0" ;
report "9th Pixel bx15 ERROR: expected r38 is 040b" ;
end if;
wait for 20 ns;
if(gs=x"87") then
report "10th Pixel RIGHT, the DUT output gs is 87" ;
else
report "10th Pixel ERROR: expected gs is 85" ;
report "10th Pixel rx38 ERROR: expected r38 is 1b9c" ;
report "10th Pixel gx75 ERROR: expected r38 is 23be" ;
report "10th Pixel bx15 ERROR: expected r38 is 0474" ;
end if;
wait for 100 ns;
wait ;
end process;
end tb;
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