Verilog coding!! I wrap the components like --- ////////////////////////////////
ID: 2290816 • Letter: V
Question
Verilog coding!!
I wrap the components like ---
//////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module wrapper (
I0, I1, I2, I3, S0, S1, Y0, Y1, Y2, Y3
);
input I3, I2, I1, I0, S1, S0;
output Y0, Y1, Y2, Y3;
// Structural Description of wrapper
wire sdata;
mux input_mux (
.I3(I3),
.I2(I2),
.I1(I1),
.I0(I0),
.S1(S1),
.S0(S0),
.Y(tData)
);
demux output_demux (
.En(tData),
.I1(S1),
.I0(S0),
.Y0(Y0),
.Y1(Y1),
.Y2(Y2),
.Y3(Y3)
);
counter counter (
.clk(Clk),
.Y0(S0),
.Y1(S1)
);
latch latch (
// .I0(Y0),
// .I1(Y1),
// .I2(Y2),
// .I3(Y3),
// .S0(Y0),
// .S1(Y1),
// .O0(Y0),
// .O1(Y1),
// .O2(Y2),
// .O3(Y3)
);
endmodule
but it doesn't work.
Diagram looks like this.
Could anyone help me?
Latch & counter looks like this. (Mux & demux works well)
Thank you.
Figure 4. Block diagram of a transmission systenm wrapper latch 3 03 2 O2 1 01 mux demux 13 /3 Y3 Y2 0 Y1 EN sdata I0 YO 51 clk Clk YO SO CounterExplanation / Answer
`timescale 1ns / 1ps
module wrapper (
I3, I2, I1, I0, clk, Y3, Y2, Y1, Y0
);
input I3, I2, I1, I0, clk;
output Y3, Y2, Y1, Y0;
// Structural Description of wrapper
wire tdata, ;
mux input_mux (
.I3(I3),
.I2(I2),
.I1(I1),
.I0(I0),
.S1(S1),
.S0(S0),
.Y(tData)
);
demux output_demux (
.En(tData),
.I1(S1),
.I0(S0),
.Y0(Y0),
.Y1(Y1),
.Y2(Y2),
.Y3(Y3)
);
counter counter (
.clk(Clk),
.Y0(S0),
.Y1(S1)
);
latch latch (
.I0(Y0),
.I1(Y1),
.I2(Y2),
.I3(Y3),
.S0(Y0),
.S1(Y1),
.O0(Y0),
.O1(Y1),
.O2(Y2),
.O3(Y3)
);
endmodule
This code will work. wire tdata is missing in your code. Clk is the input to your wrapper instead of S1 & S0.
And always use same sequence of input & output bits i.e, either MSB to LSB or LSB to MSB.
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