Need some help with these questions. Preparing for an exam. 1. What kind of devi
ID: 2291289 • Letter: N
Question
Need some help with these questions. Preparing for an exam.
1. What kind of device is shown in Figure 5?16?
2. How could the Set and Reset features be added to this device? Draw the connections needed on Figure
5?16.
3. A SR flip flop will remain in a Set or Reset condition once it has been triggered. This is why the SR flipflop
can also be call a _________________________?
4. What output(s) can occur in a SR flip?flop that cannot occur in a D type?
5. What does the D in the D?latch stand for?
6. A device that has only one stable output state is called a ___________________________?
7. Why are flip?flops considered to have a memory characteristic?
8. What is the purpose of a Schmitt trigger?
9. When J=1, K=0, S and R are both 0, the JK flip?flop is said to be in the ___________________ state.
10. Which of the two multivibrators described in this section is used as a clock device?
11. A 7474 IC is triggered by a (pulse/negative going edge/positive going edge).
12. If a JK flip?flop is in toggle mode and a 100Hz clock is input, what is the output frequency on Q and Q'?
13. What is the function of a pull?up resistor?
14. Describe switch bounce and how it can be eliminated.
15. List the ways that the Q, Q' outputs on a JK flip?flop can be changed.
16. How can a JK flip?flop be used as a D?type IC?
17. Is the monostable circuit used in this section retriggerable or non?retriggerable? Why?
18. Create a truth table for the SR logic symbol shown here.
19. Create a truth table for the D?Latch shown in Figure 5?18.
20. Create a truth table for the SR logic symbol shown in Figure 5?19.
21. Create a truth table for the JK logic symbol shown in Figure 5?20.
22. What are the outputs of Q and Q’ and the condition the JK is in for each of the following times?
22. Which flip?flop is also called a transparent latch?
23. Why are flip?flops often called latches?
24. Can switch bounce occur when a switch is opened?
25. How can flip?flops be used as frequency dividers?
26. Define Preset.
27. Define Clear.
28. What is the difference between level triggering, negative edge triggering, and positive edge
triggering?
Explanation / Answer
i can,t find the figure for Q1,Q2,17,18,19,20,21 so i answered for remaining questions.
Q3.
A SR flip flop will remain in a Set or Reset condition once it has been triggered. This is why the SR flipflop
can also be call a pulse generator(Multivibrator) to generate single output pulse generator.
Q4.
In an SR flipflop we found no change and undefined states which are not possible in D flipflop.
Q5.
The D stands for 'DELAY' in D latch.
Q6.
A device that has only one stable output state is called a monostable device.
Q7.
The flipflops are considered to be have memory charistics, Because when the flip flop enters into some state ,it will not change that state untill it is triggered by the new clock pulse, i.e it is maintaing that state for some time means storing that state untill for the next clock pulse.
Q8.
A Schmitt trigger circuit is also called a regenerative comparator circuit. The circuit is designed with a positive feedback and hence will have a regenerative action which will make the output switch levels. It is basically an inverting comparator circuit with a positive feedback. The purpose of the Schmitt trigger is to convert any regular or irregular shaped input waveform into a square wave output voltage or pulse. Thus, it can also be called a squaring circuit.
Q9.
When J=1, K=0, S and R are both 0, the JK flip?flop is said to be in the SET state. Because S=R=0 means no change in the output state and when J=1,K=0 whatever be the output state the flip flop simply goes to SET state.
Q11.
A 7474 IC is triggered by a positive going edge.
Q12.
If the input clock frequency is 100 hz the output changes for every 10ms and produce a square wave with period of 20ms, hence the output frequency is1/20ms that equals to 50 hz at both Q&Q'.
Q13.
A pull-up resistor is a resistor used to ensure a known state for a signal. It physically interrupt the connection of subsequent components to ground and assaign the components with known leve of voltages.
Q15. J K Q Q'
0 0 no change and state of Q&Q' is same as previous output state.
1 0 1 0
0 1 0 1
1 1 toggling the outputs of Q&Q'
Q16.
By simply connecting D input directly to J input(J=D) and inverted Dinput to K input (K=inverted D) we can use JK flip flop as D flip flop.
Q22. the explanation is same as Q15.
Q22.
The delay flip flop(D flip flop) is also called as transperant latch.
Q23.
Latch is a circuit that has two stable states and can be used to store state information, but the latch is asynchronous device which continuously changes its states. Whereas Flip flop is also a circuit that has two stable states and it is a synchronous device, so flip flops are also treated as latches.
Q25.
Frequency division means repeating output pattern for every certain duration of period. The flipflops which are used in Toggle mode produce repetation of pattern for certain period called frequency division by 2.
Q26.
When the PRESET input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock.
Q27.
When the CLEAR input is activated, the flip-flop will be reset(Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock.
Q28.
LEVEL triggering means The Flipflop responds when the clock signal is either HIGH or LOW.
POSITIVE EDGE triggering means The Flipflop responds at RISING EDGE of the clock signal.
NEGATIVE EDGE triggering means The Flipflop responds at FALLING EDGE of the clock signal.
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