2. [15] Recall that the hazard detection unit detects a load-use data hazard by

Question

2. [15] Recall that the hazard detection unit detects a load-use data hazard by checking if 1) the instruction at the EX stage is a load, and 2) the instruction at the ID stage uses the result of the load instruction. The condition is specified as follows: if (ID/EX. MemRead and (ID/EX.RegisterRt -IF/ID.RegisterRs) or ID/EX.RegisterRt 1F/ID.RegisterRt))) a. [101 For the full MIPS ISA, the condition check may cause false positives, i.e., it may report a load-use data hazard when none exists, and the pipeline does not have to stall. Give an example of MIPS code for which a false positive will appear and discuss why it is a false positive. Hint: The code may contain an I-type or J-type instruction

Explanation / Answer

Not all instructions have two register operands.

For example,

lw $9, 0($10)

addi $9, $8,1

The Rt for lw is $9 and the Rt for addi is $9. There is a match but no data dependence. (However, note that this code is very rare as addi overwrites the same register of lw.)

Another example:

lw $9, 0($10)

j target

In this case Rt of j is part of the 26-bit encoding of the target. If it happens to be $9, then there is unnecessary stall.

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