Verilog counter problem: Using the attached 4-bit up-counter module and testbenc
ID: 2292418 • Letter: V
Question
Verilog counter problem:
Using the attached 4-bit up-counter module and testbench as a template, write a Verilog module that implements a certain 4-bit counter. The module should include two more input variables: “updown” and “count2”.
If “updown” is 1, the circuit should count up (by 1s); if it is 0 it should count down (by 1s).
If “count2” has a value of 1, the circuit should instead count up by 2s; otherwise it will have no effect (the circuit counts normally up or down by 1s).
(Hint: use “if” and “else if” statements. After checking the “Resetn” value, check the value of “count2”).
Simulate the module in EDA Playground. In the testbench, use the following input signals:
Clock = 0; // initial value
updown = 1; // initially count up
count2 = 0; // count-by-2 disabled
Resetn = 0; // reset active
En = 1; // enable active
#10
Resetn = 1; // reset disabled
#40
updown = 0; // count down
#80
count2 = 1; // count-up-by-2 enabled
#40
Submit a printout your module (do not have to show the testbench) as well as a screenshot of the simulation results (waveforms).
EE 244-Verilog-4-bit up-counter iswi) ùbie ?? 244-Ver.log-4-bit up-counter.docx 14 TL Verilog module for a 4-bit up-counter with cnable and asynchronous reset. module upcounter4 (Resetn, Clock, En, o input Resetn, Clock, Eni output reg 3:01 Q output overflow always (negedge Resetn, posedge Clock) LE (Resetn) 0 4-0 also if (En) endmodule (testbench on next page) Verilog testbench module for the 4-bit up-counter module. nodule testbenchi reg Resotn, clock, En; //input variablas /7 output variables wire (3:0) / Inatantiate device under teat upcountor4 tb.Resetn (Resetn), Clock (Clock) En (En) always // generate clock signal #5 Clock- IClock; initial begin Dump wavesfor EDA Playground simulator Sdumpfile ("durp.ved") dunpvars(, toatbanch) // Enter input values here Clock 0 // initial value / resot // disable reset En1i #10 #50 #20 Resetn1 // resct Resetn -1: // disable resetExplanation / Answer
module counter(Resetn,clock,En,count2,updown, Q);
input Resetn,clock,En,count2,updown;
output reg [3:0] Q;
always @( negedge Resetn, posedge clock)
if (!Resetn)
Q<=0;
else if (En)
if( count2) //if count2=1 then Q=Q+2
Q<= Q+2'b10;
else if (updown) //if count2=0 then Q<=Q+1 if updown=1 else Q<=Q-1 if updown=0;
Q<=Q+1;
else
Q<=Q-1;
endmodule
Test_bench
module tb_v;
// Inputs
reg Resetn;
reg clock;
reg En;
reg count2;
reg updown;
// Outputs
wire [3:0] Q;
// Instantiate the Unit Under Test (UUT)
counter uut (
.Resetn(Resetn),
.clock(clock),
.En(En),
.count2(count2),
.updown(updown),
.Q(Q)
);
initial begin
// Initialize Inputs
Resetn = 0;
clock = 0;
En = 1'b1;
count2 = 1'b1;
updown = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always # 5 clock=~clock;
always # 100 updown =~updown;
always # 400 Resetn=~Resetn;
always # 80 count2=~count2;
endmodule
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.