Serial-adder Serial-subtractor module serial(A, B. start, resetn, clock, sum); i

Question

Serial-adder Serial-subtractor module serial(A, B. start, resetn, clock, sum); input [7:0]A, B input resetn, start, clock; output [8:0] sum // Registers wire 17:0] A reg,B_reg reg cin; ll Wires wire reset, enable, load; wire bit_sum, bit carry; Il Control FSM FSM my_control(start, clock, resetn, reset, enable, load); // Datapath shift reg reg_A(clock, l'b0, A, I'b0, enable, load, A_reg); shift reg reg B( clock, I'b0, B, 1'b0, enable, load, B_reg); II a full adder assign {bit carry, bit_sum-A reg[O+B_reg[O]+cin; always @(posedge clock) in if (enable) if (reset) cin

Explanation / Answer

serial-subtractor

module serial(A, B, start, resetn, clock, diff);

input [7:0] A,B;

input resetn, start, clock;

output [8:0] diff;

//Registers

Wire [7:0] A_reg, B_reg;

reg bin;

//Wires

Wire reset, enable, load;

Wire bit_diff, bit_borrow;

// Control FSM

FSM my_control(start, clock, resetn, reset, enable, load);

// Datapath

Shift_reg reg_A( clock, 1’b0, A, 1b’0, enable, load, A_reg);

Shift_reg reg_B( clock, 1’b0, B, 1b’0, enable, load, B_reg);

// a full subtractor

Assign {bit_borrow, bit_diff} = A_reg[0] – B_reg[0] – bin;

always @(posedge clock)

begin

    if(enable)

               if(reset)

                   bin <= 0’b0;

               else

               bin <= bit_borrow;

end

shift_reg reg_diff(clock, reset, 9’d0, bit_diff, enable, 1’b0, diff) ;

    defparam reg_diff.n=9;

end module

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