QUESTION 4 Problem 3 Wirite a Venlog module for an SR flipflop named SR ff Note

Question

QUESTION 4 Problem 3 Wirite a Venlog module for an SR flipflop named SR ff Note that the table for an SR latch is still relevant.Don' forget to inclode a clock lnaputs thould be S, Rcll, ouspats ahouald be Q and On (the oomplent ofQ) Use a Boolean expression based on the table for the next state. For full credit use the minimum number of lines required and use indenation to orgamize each block and use Venilog not System Verilog Your solution should be efficient, and succinct Path p Words.0 Click Sove All Answers to sove o answers

Explanation / Answer

library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity SR_FF is
PORT( S,R,CLOCK: in std_logic;
Q, QBAR: out std_logic);
end SR_FF;

Architecture behavioral of SR_FF is
begin
PROCESS(CLOCK)
variable tmp: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(S='0' and R='0')then
tmp:=tmp;
elsif(S='1' and R='1')then
tmp:='Z';
elsif(S='0' and R='1')then
tmp:='0';
else
tmp:='1';
end if;
end if;
Q <= tmp;
QBAR <= not tmp;
end PROCESS;
end behavioral;

or in another format

--The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all
;use IEEE.std_logic_unsigned.all;
---------------------------------- Entity Declarations -------------------------
entity SRFF is
port (CLK, RST, S, R : in std_logic;
Q, Qn : out std_logic);
end SRFF;
architecture RTL of SRFF is
signal FF : std_logic;
begin
process (CLK, RST)
variable SR : std_logic_vector(1 downto 0);
begin
if (RST = '0') then
FF <= '0';
elsif (CLK'event and CLK = '1') then
SR := S & R;
case SR is
when "01" => FF <= '0';
when "10" => FF <= '1';
when "11" => FF <= 'Z';
when others => FF <= FF;
end case;
end if;
end process;
Q <= FF ;
Qn <= not FF ;
end RTL;

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