Appreciate any help! Write the VHDL file for each of the circuits shown below (1
ID: 2314947 • Letter: A
Question
Appreciate any help!
Write the VHDL file for each of the circuits shown below
(1)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY example IS
PORT ( A, B, C :IN std_logic;
Z :OUT std_logic);
END example;
ARCHITECTURE beh OF example IS
BEGIN
Z <= (A OR B) AND NOT C;
END beh;
(2)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY problem IS
PORT ( A, B, C :IN std_logic;
Z :OUT std_logic);
END _______________;
ARCHITECTURE ___________ OF ________________ IS
BEGIN
Z <= ____________________________________;
END ________________;
Explanation / Answer
(1) VHDL 'example' code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY example IS
PORT ( A, B, C :IN std_logic;
Z :OUT std_logic);
END example;
ARCHITECTURE beh OF example IS
BEGIN
Z <= (A OR B) AND NOT C;
END beh;
(2) VHDL 'problem' code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY problem IS
PORT ( A, B, C :IN std_logic;
Z :OUT std_logic);
END problem;
ARCHITECTURE beh OF problem IS
BEGIN
Z <= (A NOR B) AND NOT C;
END beh;
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