Hello, I have the source code needed for these two problems. What I am having tr
ID: 2988045 • Letter: H
Question
Hello, I have the source code needed for these two problems. What I am having trouble with is writing the correct information in the test bench. Can anyone help??
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Write complete VHDL code for the D latch circuit with a CLR input shown in Figure P5.65. Use five Boolean equations-that is, one Boolean equation for signal E, one Boolean equation for each AND gate output, and one Boolean equation for each NOR gate output. Write complete VHDL code for the master-slave D flip-flop circuit with a CLR input shown in Figure P5.94. Use the following Boolean equations:Explanation / Answer
Dff- CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity d_ff_en is
Port ( c : in STD_LOGIC;
clr : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end d_ff_en;
architecture Behavioral of d_ff_en is
begin
process(c,clr)
begin
if(clr='1') then
q<='0';
elsif(c' event and c='1') then
q<=d;
end if;
end process;
end Behavioral;
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DFF-TB
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY dff1_vhd IS
END dff1_vhd;
ARCHITECTURE behavior OF dff1_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT d_ff_en
PORT(
c : IN std_logic;
clr : IN std_logic;
d : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL c : std_logic := '0';
SIGNAL clr : std_logic := '0';
SIGNAL d : std_logic := '0';
--Outputs
SIGNAL q : std_logic;
constant c_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: d_ff_en PORT MAP(c => c, clr => clr, d => d,q => q) ;
tb : PROCESS
BEGIN
c<='0';
-- Wait 100 ns for global reset to finish
wait for 5 ns;
c<='1';
-- Place stimulus here
wait for 5 ns; -- will wait forever
END PROCESS;
stim_proc: process
begin
d<='1';
-- hold reset state for 100ms.
wait for 100 ns;
d<='0';
wait for 100 ns;
end process;
END;
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Master slave DFF
--------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dmaster is
Port ( d : in std_logic;
c : in std_logic:='1';
clr : in std_logic:='0';
q : inout std_logic:='0');
end dmaster;
architecture Behavioral of dmaster is
signal f:std_logic;
signal e:std_logic:='0';
begin
f<= not c;
e<= ((e and f) or (c and d) or(d and e)) and (not clr);
q<= ((q and f) or(e and f))and (not clr);
end Behavioral;
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