The entity for a full adder is given below. Write a corresponding architecture i

Question

The entity for a full adder is given below. Write a corresponding architecture in behavioural VHDL using VHDL boolean functions. The entity for a 5 bit adder is given below: Where x, y and sum should be interpreted as signed binary numbers in twos complement notation. Write a corresponding architecture for add5 in structural form using the "full_adder" from part a as the only component. Make sure that the architecture is purely structural (zero marks will be awarded for a behavioural description). Dont forget to declare "full_adder" as a component. What range of decimal numbers can be represented by x, y and sum. Is the value on the sum output always valid? If not, under what conditions is it invalid? If the propagation delays of the full adder component are as follows: from any input to the sum output : tpd-sum = 2 ns From and input to the carry_out output : tpd-arry_out = 1 ns With the aid of a diagram, determine the worst case propagation delay for the "add5" implementation, from the x and y inputs to the sum output.

Explanation / Answer

Structural code for 5 bit full adder

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:57:20 06/19/2014
-- Design Name:
-- Module Name: add5 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity add5 is
port (x,y : in std_logic_vector(4 downto 0);
sum : out std_logic_vector(4 downto 0) );

end add5;

architecture Behavioral of add5 is

component fadder_strctrl1bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c_in : in STD_LOGIC;
sum : out STD_LOGIC;
c_out : out STD_LOGIC
           );
end component;

signal c1,c2,c3,c4,c5: std_logic;

begin

fadder_strctrl1bit2 : fadder_strctrl1bit port map(a => x(0) , b => y(0) , c_in => '0' , sum => sum(0) , c_out=>c1);
c2 <= x(0) and y(0);
fadder_strctrl1bit3 : fadder_strctrl1bit port map(a => x(1) , b => y(1) , c_in => c1 , sum => sum(1) , c_out=>c2);
fadder_strctrl1bit4 : fadder_strctrl1bit port map(a => x(2) , b => y(2) , c_in => c2 , sum => sum(2) , c_out=>c3);
fadder_strctrl1bit5 : fadder_strctrl1bit port map(a => x(3) , b => y(3) , c_in => c3 , sum => sum(3) , c_out=>c4);
fadder_strctrl1bit6 : fadder_strctrl1bit port map(a => x(4) , b => y(4) , c_in => c4 , sum => sum(4) , c_out=>c5);

end Behavioral;

*********************************************** 1 bit full adder**************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fadder_strctrl1bit is

Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c_in : in STD_LOGIC;
sum : out STD_LOGIC;
c_out : out STD_LOGIC
           );
end fadder_strctrl1bit;

architecture Behavioral of fadder_strctrl1bit is
component Xor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
component And1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
component Or1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
signal x,y,z,i,j: std_logic ;
begin
Xor3 : Xor1 port map(a => a , b=> b , c=> x );
Xor2 : Xor1 port map(a => x , b=> c_in , c=> sum );
and2 : And1 port map(a => a , b=> b , c=> y );
and3 : And1 port map(a => c_in , b=> b , c=> z );
and4 : And1 port map(a => a , b=> c_in , c=> i );
or2 : Or1 port map(a => y , b=> z , c=> j );
or3 : Or1 port map(a => j , b=> i , c=> c_out );

end Behavioral;

*************** xor and or gates **************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Xor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end Xor1;

architecture Behavioral of Xor1 is

begin

process(a,b)
begin
if(a=b) then
c<='0';
else
c<='1';
end if;
end process;

end Behavioral;

********************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity And1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end And1;

architecture Behavioral of And1 is

begin
c <= a and b;

end Behavioral;

*****************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Or1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end Or1;

architecture Behavioral of Or1 is

begin
c<= a or b;

end Behavioral;

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